732 lines
84 KiB
Text
732 lines
84 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.225711 # Number of seconds simulated
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sim_ticks 225710988500 # Number of ticks simulated
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final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 329346 # Simulator instruction rate (inst/s)
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host_op_rate 329346 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 186465123 # Simulator tick rate (ticks/s)
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host_mem_usage 304340 # Number of bytes of host memory used
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host_seconds 1210.47 # Real time elapsed on the host
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sim_insts 398664665 # Number of instructions simulated
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sim_ops 398664665 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
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system.physmem.bytes_read::total 503680 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 249088 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 249088 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3892 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7870 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1103571 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1127956 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2231526 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1103571 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1103571 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1103571 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1127956 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2231526 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7870 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 7870 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 503680 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 503680 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 549 # Per bank write bursts
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system.physmem.perBankRdBursts::1 676 # Per bank write bursts
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system.physmem.perBankRdBursts::2 471 # Per bank write bursts
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system.physmem.perBankRdBursts::3 633 # Per bank write bursts
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system.physmem.perBankRdBursts::4 474 # Per bank write bursts
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system.physmem.perBankRdBursts::5 477 # Per bank write bursts
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system.physmem.perBankRdBursts::6 563 # Per bank write bursts
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system.physmem.perBankRdBursts::7 560 # Per bank write bursts
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system.physmem.perBankRdBursts::8 470 # Per bank write bursts
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system.physmem.perBankRdBursts::9 437 # Per bank write bursts
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system.physmem.perBankRdBursts::10 354 # Per bank write bursts
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system.physmem.perBankRdBursts::11 323 # Per bank write bursts
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system.physmem.perBankRdBursts::12 430 # Per bank write bursts
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system.physmem.perBankRdBursts::13 556 # Per bank write bursts
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system.physmem.perBankRdBursts::14 473 # Per bank write bursts
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system.physmem.perBankRdBursts::15 424 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 225710901000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 7870 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 969 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1545 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 324.680906 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 194.047178 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 332.516800 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 535 34.63% 34.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 349 22.59% 57.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 192 12.43% 69.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 105 6.80% 76.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 65 4.21% 80.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 39 2.52% 83.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 33 2.14% 85.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 33 2.14% 87.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 194 12.56% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1545 # Bytes accessed per row activation
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system.physmem.totQLat 52849750 # Total ticks spent queuing
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system.physmem.totMemAccLat 200412250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 39350000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 6715.34 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 25465.34 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.02 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 6317 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 28679911.18 # Average gap between requests
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system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 6743520 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 3679500 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 34132800 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 14742137280 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 5830950375 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 130309976250 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 150927619725 # Total energy per rank (pJ)
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system.physmem_0.averagePower 668.685069 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 216780859000 # Time in different power states
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system.physmem_0.memoryStateTime::REF 7536880000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 1390733500 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 4936680 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 2693625 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 27003600 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 14742137280 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 5568136200 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 130540515000 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 150885422385 # Total energy per rank (pJ)
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system.physmem_1.averagePower 668.498114 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 217165940000 # Time in different power states
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system.physmem_1.memoryStateTime::REF 7536880000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 1005282000 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.cpu.branchPred.lookups 46155674 # Number of BP lookups
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system.cpu.branchPred.condPredicted 26673496 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 964868 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 25433927 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 21299796 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 83.745605 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 8306241 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 322 # Number of incorrect RAS predictions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 95501420 # DTB read hits
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system.cpu.dtb.read_misses 115 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 95501535 # DTB read accesses
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system.cpu.dtb.write_hits 73594615 # DTB write hits
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system.cpu.dtb.write_misses 852 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 73595467 # DTB write accesses
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system.cpu.dtb.data_hits 169096035 # DTB hits
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system.cpu.dtb.data_misses 967 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 169097002 # DTB accesses
|
|
system.cpu.itb.fetch_hits 98403660 # ITB hits
|
|
system.cpu.itb.fetch_misses 1242 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 98404902 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 215 # Number of system calls
|
|
system.cpu.numCycles 451421977 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 398664665 # Number of instructions committed
|
|
system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 4268732 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.132335 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.883131 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 447606238 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 3815739 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 771 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 3291.720604 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 167948311 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 40323.724130 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.720604 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.803643 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.803643 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 335915017 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 335915017 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 94433513 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 94433513 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 167948311 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 167948311 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 167948311 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 167948311 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1183 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1183 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 7115 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 7115 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 7115 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 7115 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 87406500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 87406500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 430164000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 430164000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 517570500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 517570500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 517570500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 517570500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 94434696 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 94434696 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 167955426 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 167955426 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 167955426 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 167955426 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73885.460693 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 73885.460693 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72515.846258 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 72515.846258 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72743.569923 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 72743.569923 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72743.569923 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 72743.569923 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 654 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 654 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 214 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2950 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2950 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2950 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2950 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70744000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 70744000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240380000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 240380000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 311124000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 311124000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 311124000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 311124000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73007.223942 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73007.223942 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75212.765957 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75212.765957 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74699.639856 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74699.639856 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74699.639856 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74699.639856 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 3187 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1919.659270 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 98398495 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 5165 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 19051.015489 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.659270 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.937334 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.937334 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 196812485 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 196812485 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 98398495 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 98398495 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 98398495 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 98398495 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 98398495 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 98398495 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 5165 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 5165 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 5165 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 5165 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 5165 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 5165 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 317382500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 317382500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 317382500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 317382500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 317382500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 317382500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 98403660 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 98403660 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 98403660 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 98403660 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 98403660 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 98403660 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.693127 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 61448.693127 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.693127 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 61448.693127 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.693127 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 61448.693127 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 3187 # number of writebacks
|
|
system.cpu.icache.writebacks::total 3187 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5165 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 5165 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 5165 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 5165 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 5165 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 5165 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312217500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 312217500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312217500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 312217500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312217500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 312217500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60448.693127 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60448.693127 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60448.693127 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 60448.693127 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60448.693127 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 60448.693127 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 4422.016724 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 4792 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 5270 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.909298 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 372.106243 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3407.923384 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 641.987096 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.011356 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104002 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.134949 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5270 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 114772 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 114772 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 3187 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 3187 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1273 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 1273 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1273 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1460 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1273 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1460 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3892 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 3892 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 841 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 841 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3892 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7870 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3892 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7870 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 235063000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 235063000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 291102500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 291102500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 67816500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 67816500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 291102500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 302879500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 593982000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 291102500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 302879500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 593982000 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 3187 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 3187 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5165 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 5165 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 5165 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9330 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 5165 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9330 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753533 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753533 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753533 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.843516 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753533 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.843516 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74932.419509 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74932.419509 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74795.092497 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74795.092497 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80637.931034 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80637.931034 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74795.092497 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76138.637506 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 75474.205845 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74795.092497 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76138.637506 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 75474.205845 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3892 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3892 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 841 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3892 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7870 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3892 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7870 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203693000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203693000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252182500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252182500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59406500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59406500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252182500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 263099500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 515282000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252182500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 263099500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 515282000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753533 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843516 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843516 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64932.419509 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64932.419509 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64795.092497 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64795.092497 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.931034 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.931034 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64795.092497 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 13288 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3958 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 3187 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5165 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13517 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 22618 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 842944 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 9330 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 9330 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 9330 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10485000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 7747500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 4733 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15740 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 15740 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503680 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 503680 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 7870 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 7870 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 7870 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 9171000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 41782250 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
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---------- End Simulation Statistics ----------
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