a8b03e4d01
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
105 lines
3 KiB
C++
105 lines
3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_STORE_SET_HH__
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#define __CPU_O3_STORE_SET_HH__
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#include <list>
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#include <map>
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#include <utility>
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#include <vector>
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#include "arch/isa_traits.hh"
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#include "cpu/inst_seq.hh"
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struct ltseqnum {
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bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
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{
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return lhs > rhs;
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}
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};
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class StoreSet
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{
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public:
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typedef unsigned SSID;
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public:
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StoreSet() { };
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StoreSet(int SSIT_size, int LFST_size);
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~StoreSet();
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void init(int SSIT_size, int LFST_size);
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void violation(Addr store_PC, Addr load_PC);
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void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
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void insertStore(Addr store_PC, InstSeqNum store_seq_num,
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unsigned tid);
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InstSeqNum checkInst(Addr PC);
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void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
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void squash(InstSeqNum squashed_num, unsigned tid);
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void clear();
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private:
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inline int calcIndex(Addr PC)
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{ return (PC >> offsetBits) & indexMask; }
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inline SSID calcSSID(Addr PC)
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{ return ((PC ^ (PC >> 10)) % LFSTSize); }
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std::vector<SSID> SSIT;
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std::vector<bool> validSSIT;
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std::vector<InstSeqNum> LFST;
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std::vector<bool> validLFST;
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std::map<InstSeqNum, int, ltseqnum> storeList;
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typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
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int SSITSize;
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int LFSTSize;
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int indexMask;
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// HACK: Hardcoded for now.
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int offsetBits;
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};
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#endif // __CPU_O3_STORE_SET_HH__
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