a8b03e4d01
arch/alpha/isa/decoder.isa: Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model. arch/alpha/isa/pal.isa: Allow IPR instructions to have flags. base/traceflags.py: Include new trace flags from the two new CPU models. cpu/SConscript: Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next). cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Update to the BaseDynInst for the new models. --HG-- extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
159 lines
5.5 KiB
C++
159 lines
5.5 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_FU_POOL_HH__
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#define __CPU_O3_FU_POOL_HH__
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#include <bitset>
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#include <list>
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#include <string>
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#include <vector>
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#include "base/sched_list.hh"
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#include "encumbered/cpu/full/op_class.hh"
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#include "sim/sim_object.hh"
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class FUDesc;
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class FuncUnit;
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/**
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* Pool of FU's, specific to the new CPU model. The old FU pool had lists of
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* free units and busy units, and whenever a FU was needed it would iterate
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* through the free units to find a FU that provided the capability. This pool
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* has lists of units specific to each of the capabilities, and whenever a FU
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* is needed, it iterates through that list to find a free unit. The previous
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* FU pool would have to be ticked each cycle to update which units became
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* free. This FU pool lets the IEW stage handle freeing units, which frees
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* them as their scheduled execution events complete. This limits units in this
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* model to either have identical issue and op latencies, or 1 cycle issue
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* latencies.
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*/
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class FUPool : public SimObject
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{
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private:
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/** Maximum op execution latencies, per op class. */
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unsigned maxOpLatencies[Num_OpClasses];
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/** Maximum issue latencies, per op class. */
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unsigned maxIssueLatencies[Num_OpClasses];
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/** Bitvector listing capabilities of this FU pool. */
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std::bitset<Num_OpClasses> capabilityList;
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/** Bitvector listing which FUs are busy. */
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std::vector<bool> unitBusy;
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/** List of units to be freed at the end of this cycle. */
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std::vector<int> unitsToBeFreed;
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/**
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* Class that implements a circular queue to hold FU indices. The hope is
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* that FUs that have been just used will be moved to the end of the queue
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* by iterating through it, thus leaving free units at the head of the
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* queue.
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*/
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class FUIdxQueue {
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public:
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/** Constructs a circular queue of FU indices. */
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FUIdxQueue()
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: idx(0), size(0)
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{ }
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/** Adds a FU to the queue. */
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inline void addFU(int fu_idx);
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/** Returns the index of the FU at the head of the queue, and changes
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* the index to the next element.
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*/
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inline int getFU();
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private:
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/** Circular queue index. */
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int idx;
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/** Size of the queue. */
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int size;
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/** Queue of FU indices. */
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std::vector<int> funcUnitsIdx;
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};
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/** Per op class queues of FUs that provide that capability. */
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FUIdxQueue fuPerCapList[Num_OpClasses];
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/** Number of FUs. */
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int numFU;
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/** Functional units. */
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std::vector<FuncUnit *> funcUnits;
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typedef std::vector<FuncUnit *>::iterator fuListIterator;
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public:
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/** Constructs a FU pool. */
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FUPool(std::string name, std::vector<FUDesc *> l);
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~FUPool();
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/** Annotates units that provide memory operations. Included only because
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* old FU pool provided this function.
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*/
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void annotateMemoryUnits(unsigned hit_latency);
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/**
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* Gets a FU providing the requested capability. Will mark the unit as busy,
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* but leaves the freeing of the unit up to the IEW stage.
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* @param capability The capability requested.
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* @return Returns -2 if the FU pool does not have the capability, -1 if
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* there is no free FU, and the FU's index otherwise.
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*/
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int getUnit(OpClass capability);
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/** Frees a FU at the end of this cycle. */
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void freeUnit(int fu_idx);
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/** Frees all FUs on the list. */
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void processFreeUnits();
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/** Returns the total number of FUs. */
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int size() { return numFU; }
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/** Debugging function used to dump FU information. */
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void dump();
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/** Returns the operation execution latency of the given capability. */
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unsigned getOpLatency(OpClass capability) {
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return maxOpLatencies[capability];
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}
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/** Returns the issue latency of the given capability. */
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unsigned getIssueLatency(OpClass capability) {
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return maxIssueLatencies[capability];
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}
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};
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#endif // __CPU_O3_FU_POOL_HH__
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