a8b03e4d01
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
397 lines
13 KiB
C++
397 lines
13 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_COMMIT_HH__
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#define __CPU_O3_COMMIT_HH__
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#include "arch/faults.hh"
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#include "cpu/inst_seq.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/exetrace.hh"
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#include "mem/memory_interface.hh"
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template <class>
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class O3ThreadState;
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/**
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* DefaultCommit handles single threaded and SMT commit. Its width is specified
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* by the parameters; each cycle it tries to commit that many instructions. The
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* SMT policy decides which thread it tries to commit instructions from. Non-
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* speculative instructions must reach the head of the ROB before they are
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* ready to execute; once they reach the head, commit will broadcast the
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* instruction's sequence number to the previous stages so that they can issue/
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* execute the instruction. Only one non-speculative instruction is handled per
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* cycle. Commit is responsible for handling all back-end initiated redirects.
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* It receives the redirect, and then broadcasts it to all stages, indicating
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* the sequence number they should squash until, and any necessary branch mis-
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* prediction information as well. It priortizes redirects by instruction's age,
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* only broadcasting a redirect if it corresponds to an instruction that should
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* currently be in the ROB. This is done by tracking the sequence number of the
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* youngest instruction in the ROB, which gets updated to any squashing
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* instruction's sequence number, and only broadcasting a redirect if it
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* corresponds to an older instruction. Commit also supports multiple cycle
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* squashing, to model a ROB that can only remove a certain number of
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* instructions per cycle. Eventually traps and interrupts will most likely
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* be handled here as well.
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*/
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template<class Impl>
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class DefaultCommit
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{
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public:
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// Typedefs from the Impl.
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::Params Params;
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typedef typename Impl::CPUPol CPUPol;
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typedef typename CPUPol::RenameMap RenameMap;
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typedef typename CPUPol::ROB ROB;
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typedef typename CPUPol::TimeStruct TimeStruct;
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typedef typename CPUPol::FetchStruct FetchStruct;
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typedef typename CPUPol::IEWStruct IEWStruct;
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typedef typename CPUPol::RenameStruct RenameStruct;
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typedef typename CPUPol::IEW IEW;
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typedef O3ThreadState<Impl> Thread;
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class TrapEvent : public Event {
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private:
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DefaultCommit<Impl> *commit;
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unsigned tid;
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public:
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TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
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void process();
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const char *description();
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};
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/** Overall commit status. Used to determine if the CPU can deschedule
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* itself due to a lack of activity.
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*/
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enum CommitStatus{
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Active,
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Inactive
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};
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/** Individual thread status. */
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enum ThreadStatus {
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Running,
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Idle,
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ROBSquashing,
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TrapPending,
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FetchTrapPending
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};
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/** Commit policy for SMT mode. */
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enum CommitPolicy {
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Aggressive,
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RoundRobin,
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OldestReady
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};
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private:
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/** Overall commit status. */
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CommitStatus _status;
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/** Next commit status, to be set at the end of the cycle. */
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CommitStatus _nextStatus;
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/** Per-thread status. */
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ThreadStatus commitStatus[Impl::MaxThreads];
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/** Commit policy used in SMT mode. */
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CommitPolicy commitPolicy;
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public:
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/** Construct a DefaultCommit with the given parameters. */
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DefaultCommit(Params *params);
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/** Returns the name of the DefaultCommit. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Sets the CPU pointer. */
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void setCPU(FullCPU *cpu_ptr);
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/** Sets the list of threads. */
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void setThreads(std::vector<Thread *> &threads);
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/** Sets the main time buffer pointer, used for backwards communication. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
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/** Sets the pointer to the queue coming from rename. */
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void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
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/** Sets the pointer to the queue coming from IEW. */
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void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
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/** Sets the poitner to the IEW stage. */
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void setIEWStage(IEW *iew_stage);
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/** The pointer to the IEW stage. Used solely to ensure that syscalls do
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* not execute until all stores have written back.
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*/
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IEW *iewStage;
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/** Sets pointer to list of active threads. */
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void setActiveThreads(std::list<unsigned> *at_ptr);
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/** Sets pointer to the commited state rename map. */
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void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
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/** Sets pointer to the ROB. */
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void setROB(ROB *rob_ptr);
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/** Initializes stage by sending back the number of free entries. */
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void initStage();
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/** Ticks the commit stage, which tries to commit instructions. */
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void tick();
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/** Handles any squashes that are sent from IEW, and adds instructions
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* to the ROB and tries to commit instructions.
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*/
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void commit();
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/** Returns the number of free ROB entries for a specific thread. */
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unsigned numROBFreeEntries(unsigned tid);
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void generateXCEvent(unsigned tid);
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private:
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/** Updates the overall status of commit with the nextStatus, and
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* tell the CPU if commit is active/inactive. */
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void updateStatus();
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/** Sets the next status based on threads' statuses, which becomes the
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* current status at the end of the cycle.
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*/
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void setNextStatus();
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/** Checks if the ROB is completed with squashing. This is for the case
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* where the ROB can take multiple cycles to complete squashing.
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*/
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bool robDoneSquashing();
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/** Returns if any of the threads have the number of ROB entries changed
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* on this cycle. Used to determine if the number of free ROB entries needs
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* to be sent back to previous stages.
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*/
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bool changedROBEntries();
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void squashFromTrap(unsigned tid);
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void squashFromXC(unsigned tid);
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void squashInFlightInsts(unsigned tid);
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private:
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/** Commits as many instructions as possible. */
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void commitInsts();
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/** Tries to commit the head ROB instruction passed in.
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* @param head_inst The instruction to be committed.
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*/
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bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
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void generateTrapEvent(unsigned tid);
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/** Gets instructions from rename and inserts them into the ROB. */
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void getInsts();
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/** Marks completed instructions using information sent from IEW. */
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void markCompletedInsts();
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/** Gets the thread to commit, based on the SMT policy. */
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int getCommittingThread();
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/** Returns the thread ID to use based on a round robin policy. */
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int roundRobin();
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/** Returns the thread ID to use based on an oldest instruction policy. */
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int oldestReady();
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public:
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/** Returns the PC of the head instruction of the ROB. */
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uint64_t readPC();
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uint64_t readPC(unsigned tid) { return PC[tid]; }
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void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
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uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
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void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
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/** Sets that the ROB is currently squashing. */
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void setSquashing(unsigned tid);
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private:
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to write information heading to previous stages. */
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typename TimeBuffer<TimeStruct>::wire toIEW;
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/** Wire to read information from IEW (for ROB). */
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typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
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TimeBuffer<FetchStruct> *fetchQueue;
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typename TimeBuffer<FetchStruct>::wire fromFetch;
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/** IEW instruction queue interface. */
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TimeBuffer<IEWStruct> *iewQueue;
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/** Wire to read information from IEW queue. */
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typename TimeBuffer<IEWStruct>::wire fromIEW;
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/** Rename instruction queue interface, for ROB. */
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TimeBuffer<RenameStruct> *renameQueue;
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/** Wire to read information from rename queue. */
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typename TimeBuffer<RenameStruct>::wire fromRename;
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public:
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/** ROB interface. */
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ROB *rob;
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private:
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/** Pointer to FullCPU. */
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FullCPU *cpu;
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/** Memory interface. Used for d-cache accesses. */
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MemInterface *dcacheInterface;
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std::vector<Thread *> thread;
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private:
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Fault fetchFault;
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InstSeqNum fetchFaultSN;
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int fetchTrapWait;
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/** Records that commit has written to the time buffer this cycle. Used for
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* the CPU to determine if it can deschedule itself if there is no activity.
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*/
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bool wroteToTimeBuffer;
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/** Records if the number of ROB entries has changed this cycle. If it has,
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* then the number of free entries must be re-broadcast.
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*/
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bool changedROBNumEntries[Impl::MaxThreads];
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/** A counter of how many threads are currently squashing. */
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int squashCounter;
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/** Records if a thread has to squash this cycle due to a trap. */
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bool trapSquash[Impl::MaxThreads];
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/** Records if a thread has to squash this cycle due to an XC write. */
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bool xcSquash[Impl::MaxThreads];
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/** Priority List used for Commit Policy */
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std::list<unsigned> priority_list;
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/** IEW to Commit delay, in ticks. */
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unsigned iewToCommitDelay;
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/** Commit to IEW delay, in ticks. */
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unsigned commitToIEWDelay;
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/** Rename to ROB delay, in ticks. */
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unsigned renameToROBDelay;
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unsigned fetchToCommitDelay;
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/** Rename width, in instructions. Used so ROB knows how many
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* instructions to get from the rename instruction queue.
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*/
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unsigned renameWidth;
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/** IEW width, in instructions. Used so ROB knows how many
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* instructions to get from the IEW instruction queue.
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*/
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unsigned iewWidth;
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/** Commit width, in instructions. */
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unsigned commitWidth;
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/** Number of Reorder Buffers */
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unsigned numRobs;
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/** Number of Active Threads */
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unsigned numThreads;
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Tick trapLatency;
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Tick fetchTrapLatency;
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Tick fetchFaultTick;
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Addr PC[Impl::MaxThreads];
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Addr nextPC[Impl::MaxThreads];
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/** The sequence number of the youngest valid instruction in the ROB. */
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InstSeqNum youngestSeqNum[Impl::MaxThreads];
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/** Pointer to the list of active threads. */
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std::list<unsigned> *activeThreads;
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/** Rename map interface. */
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RenameMap *renameMap[Impl::MaxThreads];
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/** Stat for the total number of committed instructions. */
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Stats::Scalar<> commitCommittedInsts;
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/** Stat for the total number of squashed instructions discarded by commit.
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*/
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Stats::Scalar<> commitSquashedInsts;
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/** Stat for the total number of times commit is told to squash.
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* @todo: Actually increment this stat.
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*/
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Stats::Scalar<> commitSquashEvents;
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/** Stat for the total number of times commit has had to stall due to a non-
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* speculative instruction reaching the head of the ROB.
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*/
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Stats::Scalar<> commitNonSpecStalls;
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/** Stat for the total number of committed branches. */
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Stats::Scalar<> commitCommittedBranches;
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/** Stat for the total number of committed loads. */
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Stats::Scalar<> commitCommittedLoads;
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/** Stat for the total number of committed memory references. */
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Stats::Scalar<> commitCommittedMemRefs;
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/** Stat for the total number of branch mispredicts that caused a squash. */
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Stats::Scalar<> branchMispredicts;
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/** Distribution of the number of committed instructions each cycle. */
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Stats::Distribution<> numCommittedDist;
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};
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#endif // __CPU_O3_COMMIT_HH__
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