a8b03e4d01
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
180 lines
4.5 KiB
C++
180 lines
4.5 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_ALPHA_PARAMS_HH__
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#define __CPU_O3_ALPHA_PARAMS_HH__
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#include "cpu/o3/cpu.hh"
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//Forward declarations
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class AlphaDTB;
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class AlphaITB;
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class FUPool;
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class FunctionalMemory;
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class MemInterface;
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class Process;
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class System;
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/**
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* This file defines the parameters that will be used for the AlphaFullCPU.
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* This must be defined externally so that the Impl can have a params class
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* defined that it can pass to all of the individual stages.
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*/
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class AlphaSimpleParams : public BaseFullCPU::Params
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{
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public:
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#if FULL_SYSTEM
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AlphaITB *itb; AlphaDTB *dtb;
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#else
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std::vector<Process *> workload;
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Process *process;
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#endif // FULL_SYSTEM
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//Page Table
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// PageTable *pTable;
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FunctionalMemory *mem;
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//
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// Caches
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//
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MemInterface *icacheInterface;
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MemInterface *dcacheInterface;
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unsigned cachePorts;
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//
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// Fetch
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//
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unsigned decodeToFetchDelay;
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unsigned renameToFetchDelay;
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unsigned iewToFetchDelay;
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unsigned commitToFetchDelay;
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unsigned fetchWidth;
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//
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// Decode
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//
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unsigned renameToDecodeDelay;
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unsigned iewToDecodeDelay;
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unsigned commitToDecodeDelay;
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unsigned fetchToDecodeDelay;
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unsigned decodeWidth;
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//
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// Rename
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//
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unsigned iewToRenameDelay;
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unsigned commitToRenameDelay;
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unsigned decodeToRenameDelay;
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unsigned renameWidth;
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//
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// IEW
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//
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unsigned commitToIEWDelay;
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unsigned renameToIEWDelay;
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unsigned issueToExecuteDelay;
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unsigned issueWidth;
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unsigned executeWidth;
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unsigned executeIntWidth;
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unsigned executeFloatWidth;
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unsigned executeBranchWidth;
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unsigned executeMemoryWidth;
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FUPool *fuPool;
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//
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// Commit
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//
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unsigned iewToCommitDelay;
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unsigned renameToROBDelay;
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unsigned commitWidth;
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unsigned squashWidth;
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//
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// Branch predictor (BP & BTB)
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//
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unsigned localPredictorSize;
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unsigned localCtrBits;
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unsigned localHistoryTableSize;
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unsigned localHistoryBits;
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unsigned globalPredictorSize;
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unsigned globalCtrBits;
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unsigned globalHistoryBits;
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unsigned choicePredictorSize;
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unsigned choiceCtrBits;
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unsigned BTBEntries;
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unsigned BTBTagSize;
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unsigned RASSize;
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//
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// Load store queue
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//
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unsigned LQEntries;
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unsigned SQEntries;
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//
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// Memory dependence
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//
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unsigned SSITSize;
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unsigned LFSTSize;
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//
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// Miscellaneous
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//
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unsigned numPhysIntRegs;
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unsigned numPhysFloatRegs;
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unsigned numIQEntries;
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unsigned numROBEntries;
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//SMT Parameters
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unsigned smtNumFetchingThreads;
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std::string smtFetchPolicy;
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std::string smtIQPolicy;
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unsigned smtIQThreshold;
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std::string smtLSQPolicy;
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unsigned smtLSQThreshold;
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std::string smtCommitPolicy;
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std::string smtROBPolicy;
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unsigned smtROBThreshold;
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// Probably can get this from somewhere.
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unsigned instShiftAmt;
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};
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#endif // __CPU_O3_ALPHA_PARAMS_HH__
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