a896960cbf
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.
arch/alpha/alpha_memory.cc:
The regfile has been changed so it no longer has the opcode and ra. Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
Moved code that once existed within simpleCPU to ev5, and templatized it.
This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
Removed opcode and ra from the regfile. The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
Added in a more generic trap function so "ev5_trap" doesn't need to be called. It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
Exec context now has the instruction within it. Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
Added declaration for execute() using FastCPUExecContext.
--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
105 lines
2.7 KiB
C++
105 lines
2.7 KiB
C++
/* $Id$ */
|
|
|
|
#ifndef __EV5_H__
|
|
#define __EV5_H__
|
|
|
|
#ifndef SYSTEM_EV5
|
|
#error This code is only valid for EV5 systems
|
|
#endif
|
|
|
|
#include "targetarch/isa_traits.hh"
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
//
|
|
//
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
//
|
|
//
|
|
|
|
#define MODE2MASK(X) (1 << (X))
|
|
|
|
// Alpha IPR register accessors
|
|
#define PC_PAL(X) ((X) & 0x1)
|
|
#define MCSR_SP(X) (((X) >> 1) & 0x3)
|
|
|
|
#define ICSR_SDE(X) (((X) >> 30) & 0x1)
|
|
#define ICSR_SPE(X) (((X) >> 28) & 0x3)
|
|
#define ICSR_FPE(X) (((X) >> 26) & 0x1)
|
|
|
|
#define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
|
|
|
|
#define DTB_CM_CM(X) (((X) >> 3) & 0x3)
|
|
#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
|
|
#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
|
|
#define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
|
|
#define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
|
|
#define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
|
|
#define DTB_PTE_FONW(X) (((X) >> 2) & 0x1)
|
|
#define DTB_PTE_GH(X) (((X) >> 5) & 0x3)
|
|
#define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
|
|
|
|
#define ICM_CM(X) (((X) >> 3) & 0x3)
|
|
#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
|
|
#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
|
|
#define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
|
|
#define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
|
|
#define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
|
|
#define ITB_PTE_GH(X) (((X) >> 5) & 0x3)
|
|
#define ITB_PTE_ASMA(X) (((X) >> 4) & 0x1)
|
|
|
|
#define VA_UNIMPL_MASK ULL(0xfffff80000000000)
|
|
#define VA_IMPL_MASK ULL(0x000007ffffffffff)
|
|
#define VA_IMPL(X) ((X) & VA_IMPL_MASK)
|
|
#define VA_VPN(X) (VA_IMPL(X) >> 13)
|
|
#define VA_SPACE(X) (((X) >> 41) & 0x3)
|
|
#define VA_POFS(X) ((X) & 0x1fff)
|
|
|
|
#define PA_IMPL_MASK ULL(0xffffffffff)
|
|
#define PA_UNCACHED_BIT ULL(0x8000000000)
|
|
#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000))
|
|
|
|
#define PA_PFN2PA(X) ((X) << 13)
|
|
|
|
|
|
#define MM_STAT_BAD_VA_MASK 0x0020
|
|
#define MM_STAT_DTB_MISS_MASK 0x0010
|
|
#define MM_STAT_FONW_MASK 0x0008
|
|
#define MM_STAT_FONR_MASK 0x0004
|
|
#define MM_STAT_ACV_MASK 0x0002
|
|
#define MM_STAT_WR_MASK 0x0001
|
|
|
|
#define OPCODE(X) (X >> 26) & 0x3f
|
|
#define RA(X) (X >> 21) & 0x1f
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
//
|
|
//
|
|
|
|
// VPTE size for HW_LD/HW_ST
|
|
#define HW_VPTE ((inst >> 11) & 0x1)
|
|
|
|
// QWORD size for HW_LD/HW_ST
|
|
#define HW_QWORD ((inst >> 12) & 0x1)
|
|
|
|
// ALT mode for HW_LD/HW_ST
|
|
#define HW_ALT (((inst >> 14) & 0x1) ? ALTMODE : 0)
|
|
|
|
// LOCK/COND mode for HW_LD/HW_ST
|
|
#define HW_LOCK (((inst >> 10) & 0x1) ? LOCKED : 0)
|
|
#define HW_COND (((inst >> 10) & 0x1) ? LOCKED : 0)
|
|
|
|
// PHY size for HW_LD/HW_ST
|
|
#define HW_PHY (((inst >> 15) & 0x1) ? PHYSICAL : 0)
|
|
|
|
// OFFSET for HW_LD/HW_ST
|
|
#define HW_OFS (inst & 0x3ff)
|
|
|
|
|
|
#define PAL_BASE 0x4000
|
|
|
|
#endif //__EV5_H__
|