d30262d480
arch/mips/isa/formats/int.format:
Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
their reg-reg counterparts
--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
36 lines
1.3 KiB
Text
36 lines
1.3 KiB
Text
def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'shw' : ('signed int', 16),
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'uhw' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sdw' : ('signed int', 64),
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'udw' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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'qf' : ('float', 128)
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}};
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def operands {{
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'Rd': IntRegOperandTraits('uw', 'RD', 'IsInteger', 1),
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'Rs': IntRegOperandTraits('uw', 'RS', 'IsInteger', 2),
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'Rt': IntRegOperandTraits('uw', 'RT', 'IsInteger', 3),
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'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3),
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'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4),
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'Fd': FloatRegOperandTraits('sf', 'FD', 'IsFloating', 1),
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'Fs': FloatRegOperandTraits('sf', 'FS', 'IsFloating', 2),
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'Ft': FloatRegOperandTraits('sf', 'FT', 'IsFloating', 3),
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'Mem': MemOperandTraits('udw', None,
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('IsMemRef', 'IsLoad', 'IsStore'), 4)
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#'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
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#'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
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#'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
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# The next two are hacks for non-full-system call-pal emulation
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#'R0': IntRegOperandTraits('uq', '0', None, 1),
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#'R16': IntRegOperandTraits('uq', '16', None, 1)
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}};
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