754 lines
24 KiB
Text
754 lines
24 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// The actual MIPS32 ISA decoder
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// -----------------------------
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// The following instructions are specified in the MIPS32 ISA
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// Specification. Decoding closely follows the style specified
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// in the MIPS32 ISAthe specification document starting with Table
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// A-2 (document available @ www.mips.com)
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//
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//@todo: Distinguish "unknown/future" use insts from "reserved"
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// ones
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decode OPCODE_HI default FailUnimpl::unknown() {
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// Derived From ... Table A-2 MIPS32 ISA Manual
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0x0: decode OPCODE_LO default FailUnimpl::reserved(){
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0x0: decode FUNCTION_HI {
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0x0: decode FUNCTION_LO {
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0x1: decode MOVCI {
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format BasicOp {
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0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
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1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
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}
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}
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format BasicOp {
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//Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
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//are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
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0x0: sll({{ Rd = Rt.uw << SA; }});
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0x2: decode SRL {
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0: srl({{ Rd = Rt.uw >> SA; }});
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//Hardcoded assuming 32-bit ISA, probably need parameter here
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1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
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}
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0x3: sra({{ Rd = Rt.sw >> SA; }});
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0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
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0x6: decode SRLV {
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0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
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//Hardcoded assuming 32-bit ISA, probably need parameter here
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1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
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}
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0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
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}
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}
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0x1: decode FUNCTION_LO {
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//Table A-3 Note: "Specific encodings of the hint field are used
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//to distinguish JR from JR.HB and JALR from JALR.HB"
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format Jump {
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0x0: jr(IsReturn);
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0x1: jalr(IsCall,IsReturn);
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}
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format BasicOp {
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0x2: movz({{ if (Rt == 0) Rd = Rs; }});
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0x3: movn({{ if (Rt != 0) Rd = Rs; }});
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}
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format Trap {
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0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
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0x5: break({{ }});
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0x7: sync({{ }});
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}
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}
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0x2: decode FUNCTION_LO {
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format BasicOp {
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0x0: mfhi({{ Rd = xc->miscRegs.hi; }});
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0x1: mthi({{ xc->miscRegs.hi = Rs; }});
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0x2: mflo({{ Rd = xc->miscRegs.lo; }});
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0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
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}
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};
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0x3: decode FUNCTION_LO {
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format IntOp {
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0x0: mult({{
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INT64 temp1 = Rs.sw * Rt.sw;
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xc->miscRegs.hi->temp1<63:32>;
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xc->miscRegs.lo->temp1<31:0>
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}});
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0x1: multu({{
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INT64 temp1 = Rs.uw * Rt.uw;
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xc->miscRegs.hi->temp1<63:32>;
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xc->miscRegs.lo->temp1<31:0>
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Rd.sw = Rs.uw * Rt.uw;
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}});
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0x2: div({{
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xc->miscRegs.hi = Rs.sw % Rt.sw;
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xc->miscRegs.lo = Rs.sw / Rt.sw;
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}});
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0x3: divu({{
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xc->miscRegs.hi = Rs.uw % Rt.uw;
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xc->miscRegs.lo = Rs.uw / Rt.uw;
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}});
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}
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};
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0x4: decode FUNCTION_LO {
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format IntOp {
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0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}});
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0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
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0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
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0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});
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0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
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0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
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0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
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0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
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}
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}
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0x5: decode FUNCTION_LO {
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format IntOp{
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0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
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0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
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}
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};
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0x6: decode FUNCTION_LO {
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format Trap {
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0x0: tge({{ }});
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0x1: tgeu({{ }});
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0x2: tlt({{ }});
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0x3: tltu({{ }});
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0x4: teq({{ }});
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0x6: tne({{ }});
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}
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}
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}
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0x1: decode REGIMM_HI {
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0x0: decode REGIMM_LO {
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format Branch {
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0x0: bltz({{ cond = (Rs.sq < 0); }});
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0x1: bgez({{ cond = (Rs.sq >= 0); }});
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//MIPS obsolete instructions
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0x2: bltzl({{ cond = (Rs.sq < 0); }});
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0x3: bgezl({{ cond = (Rs.sq >= 0); }});
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}
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}
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0x1: decode REGIMM_LO {
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format Trap {
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0x0: tgei({{ }});
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0x1: tgeiu({{ }});
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0x2: tlti({{ }});
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0x3: tltiu({{ }});
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0x4: teqi({{ }});
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0x6: tnei({{ }});
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}
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}
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0x2: decode REGIMM_LO {
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format Branch {
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0x0: bltzal({{ cond = (Rs.sq < 0); }});
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0x1: bgezal({{ cond = (Rs.sq >= 0); }});
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//MIPS obsolete instructions
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0x2: bltzall({{ cond = (Rs.sq < 0); }});
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0x3: bgezall({{ cond = (Rs.sq >= 0); }});
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}
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}
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0x3: decode REGIMM_LO {
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format Trap {
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0x7: synci({{ }});
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}
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}
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}
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format Jump {
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0x2: j();
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0x3: jal(IsCall);
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}
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format Branch {
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0x4: beq({{ cond = (Rs.sq == 0); }});
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0x5: bne({{ cond = (Rs.sq != 0); }});
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0x6: blez({{ cond = (Rs.sq <= 0); }});
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0x7: bgtz({{ cond = (Rs.sq > 0); }});
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}
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};
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0x1: decode OPCODE_LO default FailUnimpl::reserved(){
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format IntOp {
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0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
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0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
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0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }});
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0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }});
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0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
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0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
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0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
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0x7: lui({{ Rt = INTIMM << 16}});
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};
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};
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0x2: decode OPCODE_LO default FailUnimpl::reserved(){
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//Table A-11 MIPS32 COP0 Encoding of rs Field
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0x0: decode RS_MSB {
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0x0: decode RS {
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format BasicOp {
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0x0: mfc0({{
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//The contents of the coprocessor 0 register specified by the
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//combination of rd and sel are loaded into general register
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//rt. Note that not all coprocessor 0 registers support the
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//sel field. In those instances, the sel field must be zero.
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if (SEL > 0)
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panic("Can't Handle Cop0 with register select yet\n");
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uint64_t reg_num = Rd.uw;
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Rt = xc->miscRegs.cop0[reg_num];
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}});
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0xC: mtc0({{
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//The contents of the coprocessor 0 register specified by the
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//combination of rd and sel are loaded into general register
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//rt. Note that not all coprocessor 0 registers support the
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//sel field. In those instances, the sel field must be zero.
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if (SEL > 0)
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panic("Can't Handle Cop0 with register select yet\n");
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uint64_t reg_num = Rd.uw;
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xc->miscRegs.cop0[reg_num] = Rt;
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}});
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0xA: rdpgpr({{
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//Accessing Previous Shadow Set Register Number
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uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
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uint64_t reg_num = Rt.uw;
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Rd = xc->shadowIntRegFile[prev][reg_num];
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}});
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}
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0xB: decode SC {
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format BasicOp {
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0x0: di({{
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//Accessing Coprocessor 0 "Status" Register
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Rt.sw = xc->miscRegs.cop0[12];
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xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 0;
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}});
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0x1: ei({{
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//Accessing Coprocessor 0 "Status" Register
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Rt.sw = xc->miscRegs.cop0[12];
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xc->miscRegs.cop0[12][INTERRUPT_ENABLE] = 1;
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}});
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}
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}
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0xE: BasicOp::wrpgpr({{
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//Accessing Previous Shadow Set Register Number
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uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
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uint64_t reg_num = Rd.uw;
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xc->shadowIntRegFile[prev][reg_num] = Rt;
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}});
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}
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//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
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0x1: decode FUNCTION {
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format Trap {
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0x01: tlbr({{ }});
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0x02: tlbwi({{ }});
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0x06: tlbwr({{ }});
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0x08: tlbp({{ }});
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}
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format WarnUnimpl {
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0x18: eret({{ }});
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0x1F: deret({{ }});
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0x20: wait({{ }});
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}
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}
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}
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//Table A-13 MIPS32 COP1 Encoding of rs Field
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0x1: decode RS_MSB {
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0x0: decode RS_HI {
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0x0: decode RS_LO {
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format FloatOp {
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0x0: mfc1({{ Rt = Fs<31:0>; }});
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0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}});
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0x3: mfhc1({{ Rt = Fs<63:32>;}});
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0x4: mtc1({{ Fs<31:0> = Rt}});
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0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}});
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0x7: mftc1({{ Fs<63:32> = Rt}});
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}
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}
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0x1: decode ND {
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0x0: decode TF {
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format Branch {
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0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
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0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
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}
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}
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0x1: decode TF {
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format Branch {
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0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
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0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
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}
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}
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}
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}
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0x1: decode RS_HI {
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0x2: decode RS_LO {
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//Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
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//(( single-word ))
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0x0: decode RS_HI {
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0x0: decode RS_LO {
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format FloatOp {
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0x0: add_fmt({{ }});
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0x1: sub_fmt({{ }});
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0x2: mul_fmt({{ }});
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0x3: div_fmt({{ }});
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0x4: sqrt_fmt({{ }});
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0x5: abs_fmt({{ }});
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0x6: mov_fmt({{ }});
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0x7: neg_fmt({{ }});
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}
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}
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0x1: decode RS_LO {
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//only legal for 64 bit
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format Float64Op {
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0x0: round_l({{ }});
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0x1: trunc_l({{ }});
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0x2: ceil_l({{ }});
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0x3: floor_l({{ }});
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}
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format FloatOp {
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0x4: round_w({{ }});
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0x5: trunc_w({{ }});
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0x6: ceil_w({{ }});
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0x7: floor_w({{ }});
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}
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}
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0x2: decode RS_LO {
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0x1: decode MOVCF {
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format FloatOp {
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0x0: movf_fmt({{ }});
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0x1: movt_fmt({{ }});
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}
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}
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format BasicOp {
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0x2: movz({{ if (Rt == 0) Rd = Rs; }});
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0x3: movn({{ if (Rt != 0) Rd = Rs; }});
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}
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format Float64Op {
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0x2: recip({{ }});
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0x3: rsqrt{{ }});
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}
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}
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0x4: decode RS_LO {
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0x1: cvt_d({{ }});
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0x4: cvt_w({{ }});
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//only legal for 64 bit
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format Float64Op {
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0x5: cvt_l({{ }});
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0x6: cvt_ps({{ }});
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}
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}
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}
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//Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
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0x1: decode RS_HI {
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0x0: decode RS_LO {
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format FloatOp {
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0x0: add_fmt({{ }});
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0x1: sub_fmt({{ }});
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0x2: mul_fmt({{ }});
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0x3: div_fmt({{ }});
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0x4: sqrt_fmt({{ }});
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0x5: abs_fmt({{ }});
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0x6: mov_fmt({{ }});
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0x7: neg_fmt({{ }});
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}
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}
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0x1: decode RS_LO {
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//only legal for 64 bit
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format FloatOp64 {
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0x0: round_l({{ }});
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0x1: trunc_l({{ }});
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0x2: ceil_l({{ }});
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0x3: floor_l({{ }});
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}
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format FloatOp {
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0x4: round_w({{ }});
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0x5: trunc_w({{ }});
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0x6: ceil_w({{ }});
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0x7: floor_w({{ }});
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}
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}
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0x2: decode RS_LO {
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0x1: decode MOVCF {
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format FloatOp {
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0x0: movf_fmt({{ }});
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0x1: movt_fmt({{ }});
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}
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}
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format BasicOp {
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0x2: movz({{ if (Rt == 0) Rd = Rs; }});
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0x3: movn({{ if (Rt != 0) Rd = Rs; }});
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}
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format FloatOp64 {
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0x5: recip({{ }});
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0x6: rsqrt{{ }});
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}
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}
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0x4: decode RS_LO {
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format FloatOp {
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0x0: cvt_s({{ }});
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0x4: cvt_w({{ }});
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}
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//only legal for 64 bit
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format FloatOp64 {
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0x5: cvt_l({{ }});
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}
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}
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}
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//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
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0x4: decode FUNCTION {
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format FloatOp {
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0x10: cvt_s({{ }});
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0x10: cvt_d({{ }});
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}
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}
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//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
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//Note: "1. Format type L is legal only if 64-bit floating point operations
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//are enabled."
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0x5: decode FUNCTION_HI {
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format FloatOp {
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0x10: cvt_s({{ }});
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0x11: cvt_d({{ }});
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}
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}
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//Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
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//Note: "1. Format type PS is legal only if 64-bit floating point operations
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//are enabled. "
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0x6: decode RS_HI {
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0x0: decode RS_LO {
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format FloatOp64 {
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0x0: add_fmt({{ }});
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0x1: sub_fmt({{ }});
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0x2: mul_fmt({{ }});
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0x5: abs_fmt({{ }});
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0x6: mov_fmt({{ }});
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0x7: neg_fmt({{ }});
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}
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}
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0x2: decode RS_LO {
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0x1: decode MOVCF {
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format FloatOp64 {
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0x0: movf_fmt({{ }});
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0x1: movt_fmt({{ }});
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}
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}
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}
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0x4: decode RS_LO {
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0x0: FloatOp64::cvt_s_pu({{ }});
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}
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0x5: decode RS_LO {
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format FloatOp64 {
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0x0: cvt_s_pl({{ }});
|
|
0x4: pll_s_pl({{ }});
|
|
0x5: plu_s_pl({{ }});
|
|
0x6: pul_s_pl({{ }});
|
|
0x7: puu_s_pl({{ }});
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//Table A-19 MIPS32 COP2 Encoding of rs Field
|
|
0x2: decode RS_MSB {
|
|
0x0: decode RS_HI {
|
|
0x0: decode RS_LO {
|
|
format WarnUnimpl {
|
|
0x0: mfc2({{ }});
|
|
0x2: cfc2({{ }});
|
|
0x3: mfhc2({{ }});
|
|
0x4: mtc2({{ }});
|
|
0x6: ctc2({{ }});
|
|
0x7: mftc2({{ }});
|
|
}
|
|
}
|
|
|
|
0x1: decode ND {
|
|
0x0: decode TF {
|
|
format Branch {
|
|
0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
|
|
0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
|
|
}
|
|
}
|
|
|
|
0x1: decode TF {
|
|
format Branch {
|
|
0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
|
|
0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//Table A-20 MIPS64 COP1X Encoding of Function Field 1
|
|
//Note: "COP1X instructions are legal only if 64-bit floating point
|
|
//operations are enabled."
|
|
0x3: decode FUNCTION_HI {
|
|
0x0: decode FUNCTION_LO {
|
|
format Memory {
|
|
0x0: lwxc1({{ }});
|
|
0x1: ldxc1({{ }});
|
|
0x5: luxc1({{ }});
|
|
}
|
|
}
|
|
|
|
0x1: decode FUNCTION_LO {
|
|
format Memory {
|
|
0x0: swxc1({{ }});
|
|
0x1: sdxc1({{ }});
|
|
0x5: suxc1({{ }});
|
|
0x7: prefx({{ }});
|
|
}
|
|
}
|
|
|
|
format FloatOp {
|
|
0x3: alnv_ps({{ }});
|
|
|
|
0x4: decode FUNCTION_LO {
|
|
0x0: madd_s({{ }});
|
|
0x1: madd_d({{ }});
|
|
0x6: madd_ps({{ }});
|
|
}
|
|
|
|
0x5: decode FUNCTION_LO {
|
|
0x0: msub_s({{ }});
|
|
0x1: msub_d({{ }});
|
|
0x6: msub_ps({{ }});
|
|
}
|
|
|
|
0x6: decode FUNCTION_LO {
|
|
0x0: nmadd_s({{ }});
|
|
0x1: nmadd_d({{ }});
|
|
0x6: nmadd_ps({{ }});
|
|
}
|
|
|
|
0x7: decode FUNCTION_LO {
|
|
0x0: nmsub_s({{ }});
|
|
0x1: nmsub_d({{ }});
|
|
0x6: nmsub_ps({{ }});
|
|
}
|
|
}
|
|
}
|
|
|
|
//MIPS obsolete instructions
|
|
format Branch {
|
|
0x4: beql({{ cond = (Rs.sq == 0); }});
|
|
0x5: bnel({{ cond = (Rs.sq != 0); }});
|
|
0x6: blezl({{ cond = (Rs.sq <= 0); }});
|
|
0x7: bgtzl({{ cond = (Rs.sq > 0); }});
|
|
}
|
|
};
|
|
|
|
0x3: decode OPCODE_LO default FailUnimpl::reserved() {
|
|
|
|
//Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
|
|
0x4: decode FUNCTION_HI {
|
|
|
|
0x0: decode FUNCTION_LO {
|
|
format IntOp {
|
|
0x0: madd({{
|
|
INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
|
|
temp1 = temp1 + (Rs.sw * Rt.sw);
|
|
xc->miscRegs.hi->temp1<63:32>;
|
|
xc->miscRegs.lo->temp1<31:0>
|
|
}});
|
|
|
|
0x1: maddu({{
|
|
INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
|
|
temp1 = temp1 + (Rs.uw * Rt.uw);
|
|
xc->miscRegs.hi->temp1<63:32>;
|
|
xc->miscRegs.lo->temp1<31:0>
|
|
}});
|
|
|
|
0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
|
|
|
|
0x4: msub({{
|
|
INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
|
|
temp1 = temp1 - (Rs.sw * Rt.sw);
|
|
xc->miscRegs.hi->temp1<63:32>;
|
|
xc->miscRegs.lo->temp1<31:0>
|
|
}});
|
|
|
|
0x5: msubu({{
|
|
INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
|
|
temp1 = temp1 - (Rs.uw * Rt.uw);
|
|
xc->miscRegs.hi->temp1<63:32>;
|
|
xc->miscRegs.lo->temp1<31:0>
|
|
}});
|
|
}
|
|
}
|
|
|
|
0x4: decode FUNCTION_LO {
|
|
format BasicOp {
|
|
0x0: clz({{
|
|
int cnt = 0;
|
|
int idx = 0;
|
|
while ( Rs.uw<idx>!= 1) {
|
|
cnt++;
|
|
idx--;
|
|
}
|
|
|
|
Rd.uw = cnt;
|
|
}});
|
|
|
|
0x1: clo({{
|
|
int cnt = 0;
|
|
int idx = 0;
|
|
while ( Rs.uw<idx>!= 0) {
|
|
cnt++;
|
|
idx--;
|
|
}
|
|
|
|
Rd.uw = cnt;
|
|
}});
|
|
}
|
|
}
|
|
|
|
0x7: decode FUNCTION_LO {
|
|
0x7: WarnUnimpl::sdbbp({{ }});
|
|
}
|
|
}
|
|
|
|
//Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
|
|
0x7: decode FUNCTION_HI {
|
|
|
|
0x0: decode FUNCTION_LO {
|
|
format WarnUnimpl {
|
|
0x1: ext({{ }});
|
|
0x4: ins({{ }});
|
|
}
|
|
}
|
|
|
|
//Table A-10 MIPS32 BSHFL Encoding of sa Field
|
|
0x4: decode SA {
|
|
format BasicOp {
|
|
0x02: wsbh({{ }});
|
|
0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
|
|
0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}});
|
|
}
|
|
}
|
|
|
|
0x6: decode FUNCTION_LO {
|
|
0x7: BasicOp::rdhwr({{ }});
|
|
}
|
|
}
|
|
};
|
|
|
|
0x4: decode OPCODE_LO default FailUnimpl::reserved() {
|
|
format Memory {
|
|
0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
|
|
0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
|
|
0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
|
|
0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
|
|
0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
|
|
0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
|
|
0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
|
|
};
|
|
|
|
0x7: FailUnimpl::reserved({{ }});
|
|
};
|
|
|
|
0x5: decode OPCODE_LO default FailUnimpl::reserved() {
|
|
format Memory {
|
|
0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
|
|
0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
|
|
0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
|
|
0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
|
|
0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
|
|
};
|
|
|
|
format WarnUnimpl {
|
|
0x4: reserved({{ }});
|
|
0x5: reserved({{ }});
|
|
0x7: cache({{ }});
|
|
};
|
|
|
|
};
|
|
|
|
0x6: decode OPCODE_LO default FailUnimpl::reserved() {
|
|
format Memory {
|
|
0x0: ll({{ }});
|
|
0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
|
|
0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
|
|
};
|
|
};
|
|
|
|
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
|
|
format Memory {
|
|
0x0: sc({{ }});
|
|
0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
|
|
0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
|
|
};
|
|
|
|
}
|
|
}
|
|
|
|
|