08f7a8bc00
This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
1509 lines
172 KiB
Text
1509 lines
172 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.401336 # Number of seconds simulated
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sim_ticks 2401336466000 # Number of ticks simulated
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final_tick 2401336466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 184517 # Simulator instruction rate (inst/s)
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host_op_rate 236966 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7343776984 # Simulator tick rate (ticks/s)
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host_mem_usage 427572 # Number of bytes of host memory used
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host_seconds 326.99 # Real time elapsed on the host
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sim_insts 60334938 # Number of instructions simulated
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sim_ops 77485485 # Number of ops (including micro ops) simulated
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 500256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 7098320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 85696 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 673152 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.dtb.walker 832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 178560 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 1305852 # Number of bytes read from this memory
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system.physmem.bytes_read::total 124661996 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 500256 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 85696 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 178560 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 764512 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3746176 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 1490900 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu2.data 1325460 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6761992 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 14019 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 110945 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1339 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 10518 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.dtb.walker 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 2790 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 20418 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 14512430 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 58534 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 372725 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu2.data 331365 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 812488 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47814654 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 208324 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 2955987 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 35687 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 280324 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.dtb.walker 346 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 74359 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 543802 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51913590 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 208324 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 35687 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 74359 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 318369 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1560038 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 620863 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu2.data 551968 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2815929 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1560038 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47814654 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 208324 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 3576850 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 35687 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 363384 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 74359 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 1095770 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 54729518 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 12617991 # Total number of read requests seen
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system.physmem.writeReqs 398645 # Total number of write requests seen
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system.physmem.cpureqs 54826 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 807551424 # Total number of bytes read from memory
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system.physmem.bytesWritten 25513280 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 102907452 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 2639540 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 2346 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 789133 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 788799 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 789207 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 789032 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 788708 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 788885 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 788938 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 788613 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 788036 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 788045 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 788296 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 788257 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 788088 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 788320 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 788751 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 24965 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 24839 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 24775 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 25066 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 24855 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 24641 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 25248 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 25299 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 25161 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 24839 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 24628 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 24359 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 24939 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 24843 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 24962 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 25226 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 14345 # Number of times wr buffer was full causing retry
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system.physmem.totGap 2400301266000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 15 # Categorize read packet sizes
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system.physmem.readPktSize::3 12582912 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 35064 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 381229 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 17416 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 815827 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 792038 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 797714 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 2998166 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2260876 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2261203 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2249594 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 49322 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 91361 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 133530 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 91345 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 6960 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 6956 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 6952 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 6952 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2977 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2986 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2990 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 3015 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 3013 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 3010 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 3005 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 17339 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 17335 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 17331 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 17325 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 17311 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 17307 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 17304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 17300 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 17295 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 17291 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 17290 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 17286 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 14404 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 14384 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 14356 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 14354 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 14352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 14350 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 14348 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 14346 # What write queue length does an incoming req see
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system.physmem.totQLat 277202035000 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 353023032500 # Sum of mem lat for all requests
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system.physmem.totBusLat 63089955000 # Total cycles spent in databus access
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system.physmem.totBankLat 12731042500 # Total cycles spent in bank access
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system.physmem.avgQLat 21968.79 # Average queueing delay per request
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system.physmem.avgBankLat 1008.96 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 27977.75 # Average memory access latency
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system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 10.62 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 42.85 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 2.71 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.15 # Average read queue length over time
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system.physmem.avgWrQLen 0.39 # Average write queue length over time
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system.physmem.readRowHits 12563370 # Number of row buffer hits during reads
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system.physmem.writeRowHits 392291 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes
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system.physmem.avgGap 184402.58 # Average gap between requests
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system.l2c.replacements 63266 # number of replacements
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system.l2c.tagsinuse 50361.629322 # Cycle average of tags in use
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system.l2c.total_refs 1749187 # Total number of references to valid blocks.
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system.l2c.sampled_refs 128660 # Sample count of references to valid blocks.
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system.l2c.avg_refs 13.595422 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 2374413040000 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::writebacks 36831.903030 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.inst 5145.178956 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.data 3770.285257 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.inst 800.231814 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.data 751.654048 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu2.dtb.walker 12.723407 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu2.inst 1461.831435 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu2.data 1586.827913 # Average occupied blocks per requestor
|
|
system.l2c.occ_percent::writebacks 0.562010 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.inst 0.078509 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.data 0.057530 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.inst 0.012211 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.data 0.011469 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.dtb.walker 0.000194 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.inst 0.022306 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.data 0.024213 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::total 0.768457 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 8900 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 3213 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 461136 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 170235 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 2537 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 1106 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 134711 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 65741 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.dtb.walker 17822 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.itb.walker 4190 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 284203 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 137164 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1290958 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 597590 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 597590 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 61031 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 19032 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 33560 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 113623 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 8900 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 3213 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 461136 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 231266 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 2537 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 1106 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 134711 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 84773 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.dtb.walker 17822 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.itb.walker 4190 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 284203 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 170724 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1404581 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 8900 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 3213 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 461136 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 231266 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 2537 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 1106 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 134711 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 84773 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.dtb.walker 17822 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.itb.walker 4190 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 284203 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 170724 # number of overall hits
|
|
system.l2c.overall_hits::total 1404581 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 7403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6349 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 1339 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 1210 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.dtb.walker 13 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 2790 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 2574 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 21682 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1421 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 495 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 987 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 105359 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 9583 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 18426 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 133368 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 7403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 111708 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 1339 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 10793 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.dtb.walker 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 2790 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 21000 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 155050 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 7403 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 111708 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 1339 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 10793 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.dtb.walker 13 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 2790 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 21000 # number of overall misses
|
|
system.l2c.overall_misses::total 155050 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 76508500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 69917500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 783000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 178873500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 152904999 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 479056499 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 91500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu2.data 69000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 160500 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 429692000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 973653500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 1403345500 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 76508500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 499609500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.dtb.walker 783000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 178873500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 1126558499 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 1882401999 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 76508500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 499609500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.dtb.walker 783000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 178873500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 1126558499 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 1882401999 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 8901 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 3215 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 468539 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 176584 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 2538 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 1106 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 136050 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 66951 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.dtb.walker 17835 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.itb.walker 4190 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 286993 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 139738 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1312640 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 597590 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 597590 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 1434 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 499 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 1000 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 166390 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 28615 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 51986 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 246991 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 8901 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 3215 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 468539 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 342974 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 2538 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 1106 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 136050 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 95566 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.dtb.walker 17835 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.itb.walker 4190 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 286993 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 191724 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1559631 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 8901 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 3215 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 468539 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 342974 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 2538 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 1106 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 136050 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 95566 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.dtb.walker 17835 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.itb.walker 4190 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 286993 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 191724 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1559631 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000622 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015800 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.035955 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.009842 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.018073 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.009721 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.018420 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.016518 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990934 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991984 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.987000 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.989772 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.633205 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.334894 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 0.354442 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.539971 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000622 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.015800 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.325704 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.009842 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.112938 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.009721 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.109532 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.099415 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000622 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.015800 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.325704 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.009842 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.112938 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.009721 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.109532 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.099415 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57138.536221 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 57783.057851 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 64112.365591 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 59403.651515 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 22094.663730 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 184.848485 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 69.908815 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 55.287633 # average UpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44838.985704 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52841.284055 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 10522.355438 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 57138.536221 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 46290.141759 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 64112.365591 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 53645.642810 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 12140.612699 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 57138.536221 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 46290.141759 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 64112.365591 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 53645.642810 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 12140.612699 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 58534 # number of writebacks
|
|
system.l2c.writebacks::total 58534 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 1339 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 1210 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 13 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 2790 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.data 2566 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 7919 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 495 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 987 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 1482 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 9583 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 18426 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 28009 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 1339 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 10793 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.dtb.walker 13 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 2790 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 20992 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 35928 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 1339 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 10793 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.dtb.walker 13 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 2790 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 20992 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 35928 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56251 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59716089 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54808460 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 621263 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 144123701 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 120589158 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 379914922 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4988470 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9870987 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 14859457 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 310362321 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 743903257 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 1054265578 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 59716089 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 365170781 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 621263 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 144123701 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 864492415 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 1434180500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56251 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 59716089 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 365170781 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 621263 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 144123701 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 864492415 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 1434180500 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25160642000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26578724012 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 51739366012 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647954364 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9829694360 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 10477648724 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25808596364 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36408418372 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 62217014736 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018073 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018363 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.006033 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991984 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.987000 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.505285 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.334894 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.354442 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.113401 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.023036 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.023036 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45296.247934 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 46994.995323 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 47975.113272 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10077.717172 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.624157 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32386.759992 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40372.476772 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 37640.243422 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 8079595 # DTB read hits
|
|
system.cpu0.dtb.read_misses 6254 # DTB read misses
|
|
system.cpu0.dtb.write_hits 6630051 # DTB write hits
|
|
system.cpu0.dtb.write_misses 2055 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 5732 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 128 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 8085849 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 6632106 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 14709646 # DTB hits
|
|
system.cpu0.dtb.misses 8309 # DTB misses
|
|
system.cpu0.dtb.accesses 14717955 # DTB accesses
|
|
system.cpu0.itb.inst_hits 32707746 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 3496 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 32711242 # ITB inst accesses
|
|
system.cpu0.itb.hits 32707746 # DTB hits
|
|
system.cpu0.itb.misses 3496 # DTB misses
|
|
system.cpu0.itb.accesses 32711242 # DTB accesses
|
|
system.cpu0.numCycles 113988289 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 32205724 # Number of instructions committed
|
|
system.cpu0.committedOps 42407604 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 37554027 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 5120 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1187729 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 4239348 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 37554027 # number of integer instructions
|
|
system.cpu0.num_fp_insts 5120 # number of float instructions
|
|
system.cpu0.num_int_register_reads 191333530 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 39644160 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 3702 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1420 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 15372618 # number of memory refs
|
|
system.cpu0.num_load_insts 8447076 # Number of load instructions
|
|
system.cpu0.num_store_insts 6925542 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 13415449988.373053 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles -13301461699.373053 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction -116.691476 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 117.691476 # Percentage of idle cycles
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 82896 # number of quiesce instructions executed
|
|
system.cpu0.icache.replacements 892496 # number of replacements
|
|
system.cpu0.icache.tagsinuse 511.604237 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 44360992 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 893008 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 49.675918 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 8108819000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 478.427369 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_blocks::cpu1.inst 17.974038 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_blocks::cpu2.inst 15.202829 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.934428 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::cpu1.inst 0.035106 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::cpu2.inst 0.029693 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 32241170 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 8377396 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 3742426 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 44360992 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 32241170 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 8377396 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 3742426 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 44360992 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 32241170 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 8377396 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 3742426 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 44360992 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 469261 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 136323 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 311228 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 916812 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 469261 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 136323 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 311228 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 916812 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 469261 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 136323 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 311228 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 916812 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1838935000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4152917486 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 5991852486 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 1838935000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 4152917486 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 5991852486 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 1838935000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 4152917486 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 5991852486 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32710431 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 8513719 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 4053654 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 45277804 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 32710431 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 8513719 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 4053654 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 45277804 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 32710431 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 8513719 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 4053654 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 45277804 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014346 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016012 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076777 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.020249 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014346 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016012 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076777 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.020249 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014346 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016012 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076777 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.020249 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13489.543217 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13343.649948 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 6535.530170 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13489.543217 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13343.649948 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 6535.530170 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13489.543217 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13343.649948 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 6535.530170 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 3861 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 220 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.550000 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23796 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 23796 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 23796 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 23796 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 23796 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 23796 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 136323 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287432 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 423755 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 136323 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 287432 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 423755 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 136323 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 287432 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 423755 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1566289000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3388078986 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4954367986 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1566289000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3388078986 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4954367986 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1566289000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3388078986 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4954367986 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009359 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.009359 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.009359 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11691.585907 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11691.585907 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11691.585907 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 629752 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 23211225 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 630264 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 36.827782 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 495.729006 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_blocks::cpu1.data 9.821503 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_blocks::cpu2.data 6.446607 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.968221 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::cpu1.data 0.019183 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::cpu2.data 0.012591 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6959921 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 1905228 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 4437258 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 13302407 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 5951579 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 1349529 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 2119159 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 9420267 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131066 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34182 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72930 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 238178 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137461 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35898 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74040 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 247399 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 12911500 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 3254757 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 6556417 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 22722674 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 12911500 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 3254757 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 6556417 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 22722674 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 170189 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 65235 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 281776 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 517200 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 167824 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 29114 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 599232 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 796170 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6395 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1716 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3875 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 11986 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 338013 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 94349 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 881008 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1313370 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 338013 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 94349 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 881008 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1313370 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 910187500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4059279000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 4969466500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 718682500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18333372895 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 19052055395 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22464000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52254000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 74718000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 1628870000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 22392651895 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 24021521895 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 1628870000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 22392651895 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 24021521895 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7130110 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1970463 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4719034 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 13819607 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6119403 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1378643 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2718391 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 10216437 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137461 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35898 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76805 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 250164 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137461 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35898 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74042 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 247401 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 13249513 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 3349106 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 7437425 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 24036044 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 13249513 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 3349106 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 7437425 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 24036044 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023869 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033106 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059711 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.037425 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027425 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021118 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220436 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.077930 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046522 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047802 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050452 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047913 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025511 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028171 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118456 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.054642 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025511 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028171 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118456 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.054642 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13952.441174 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14406.049486 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 9608.403906 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24685.117126 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30594.782814 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23929.632359 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.909091 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13484.903226 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6233.772735 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 18289.988271 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 18289.988271 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 9551 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 1722 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 1090 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 46 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.762385 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 37.434783 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 597590 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 597590 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145454 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 145454 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 546284 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 546284 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 421 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 421 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 691738 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 691738 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 691738 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 691738 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65235 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 136322 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 201557 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29114 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52948 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1716 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3454 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5170 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 94349 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 189270 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 283619 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 94349 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 189270 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 283619 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779717500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1769361500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2549079000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 660454500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1423557990 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2084012490 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19032000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40419500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59451500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1440172000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3192919490 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 4633091490 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1440172000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3192919490 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 4633091490 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27487398000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29017842000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56505240000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281263000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147361293 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15428624293 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28768661000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43165203293 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71933864293 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033106 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028888 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014585 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021118 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019478 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008032 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047802 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044971 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020666 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.441174 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.280674 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12646.938583 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22685.117126 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26885.963398 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25395.584924 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.909091 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11702.229299 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11499.323017 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 2185339 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2099 # DTB read misses
|
|
system.cpu1.dtb.write_hits 1465312 # DTB write hits
|
|
system.cpu1.dtb.write_misses 382 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1728 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 2187438 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 1465694 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 3650651 # DTB hits
|
|
system.cpu1.dtb.misses 2481 # DTB misses
|
|
system.cpu1.dtb.accesses 3653132 # DTB accesses
|
|
system.cpu1.itb.inst_hits 8513719 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 1131 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 841 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 8514850 # ITB inst accesses
|
|
system.cpu1.itb.hits 8513719 # DTB hits
|
|
system.cpu1.itb.misses 1131 # DTB misses
|
|
system.cpu1.itb.accesses 8514850 # DTB accesses
|
|
system.cpu1.numCycles 574637078 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 8294211 # Number of instructions committed
|
|
system.cpu1.committedOps 10531754 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 9421872 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 319530 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 1158784 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 9421872 # number of integer instructions
|
|
system.cpu1.num_fp_insts 2078 # number of float instructions
|
|
system.cpu1.num_int_register_reads 54337439 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 10233618 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 3824850 # number of memory refs
|
|
system.cpu1.num_load_insts 2281405 # Number of load instructions
|
|
system.cpu1.num_store_insts 1543445 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 540667957.850120 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 33969120.149880 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.059114 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.940886 # Percentage of idle cycles
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.branchPred.lookups 4687055 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 3808844 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 220686 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 3132450 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 2515746 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 80.312407 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 409998 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 21415 # Number of incorrect RAS predictions.
|
|
system.cpu2.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dtb.read_hits 10844149 # DTB read hits
|
|
system.cpu2.dtb.read_misses 22603 # DTB read misses
|
|
system.cpu2.dtb.write_hits 3263914 # DTB write hits
|
|
system.cpu2.dtb.write_misses 5857 # DTB write misses
|
|
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
|
|
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dtb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dtb.align_faults 825 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch
|
|
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dtb.perms_faults 466 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dtb.read_accesses 10866752 # DTB read accesses
|
|
system.cpu2.dtb.write_accesses 3269771 # DTB write accesses
|
|
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dtb.hits 14108063 # DTB hits
|
|
system.cpu2.dtb.misses 28460 # DTB misses
|
|
system.cpu2.dtb.accesses 14136523 # DTB accesses
|
|
system.cpu2.itb.inst_hits 4055013 # ITB inst hits
|
|
system.cpu2.itb.inst_misses 4560 # ITB inst misses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
|
|
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.itb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
|
|
system.cpu2.itb.flush_entries 1575 # Number of entries that have been flushed from TLB
|
|
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.itb.perms_faults 1017 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.inst_accesses 4059573 # ITB inst accesses
|
|
system.cpu2.itb.hits 4055013 # DTB hits
|
|
system.cpu2.itb.misses 4560 # DTB misses
|
|
system.cpu2.itb.accesses 4059573 # DTB accesses
|
|
system.cpu2.numCycles 88254759 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 9429776 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 32237470 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 4687055 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 2925744 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 6801535 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 1807730 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.TlbCycles 51877 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu2.fetch.BlockedCycles 19337159 # Number of cycles fetch has spent blocked
|
|
system.cpu2.fetch.MiscStallCycles 319 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.PendingDrainCycles 987 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu2.fetch.PendingTrapStallCycles 33898 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.PendingQuiesceStallCycles 57137 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 401 # Number of stall cycles due to full MSHR
|
|
system.cpu2.fetch.CacheLines 4053658 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 309769 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 36952841 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.047181 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.432989 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 30156381 81.61% 81.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 380935 1.03% 82.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 507291 1.37% 84.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 812322 2.20% 86.21% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 657376 1.78% 87.99% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 343317 0.93% 88.92% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 1003055 2.71% 91.63% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 237893 0.64% 92.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 2854271 7.72% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 36952841 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.053108 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 0.365277 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 10041048 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 19275643 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 6155197 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 292391 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 1187539 # Number of cycles decode is squashing
|
|
system.cpu2.decode.BranchResolved 608222 # Number of times decode resolved a branch
|
|
system.cpu2.decode.BranchMispred 53447 # Number of times decode detected a branch misprediction
|
|
system.cpu2.decode.DecodedInsts 36559853 # Number of instructions handled by decode
|
|
system.cpu2.decode.SquashedInsts 181421 # Number of squashed instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 1187539 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 10612647 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 6555727 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 11181502 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 5856266 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 1558172 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 34319277 # Number of instructions processed by rename
|
|
system.cpu2.rename.ROBFullEvents 2410 # Number of times rename has blocked due to ROB full
|
|
system.cpu2.rename.IQFullEvents 422959 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LSQFullEvents 872955 # Number of times rename has blocked due to LSQ full
|
|
system.cpu2.rename.FullRegisterEvents 107 # Number of times there has been no free registers
|
|
system.cpu2.rename.RenamedOperands 36779919 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 156919879 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 156892837 # Number of integer rename lookups
|
|
system.cpu2.rename.fp_rename_lookups 27042 # Number of floating rename lookups
|
|
system.cpu2.rename.CommittedMaps 25654971 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 11124947 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 231561 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 207869 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 3330119 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 6484809 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 3835337 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 528235 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 785937 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 31561835 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 513874 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 34144653 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 53839 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 7344925 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 19731311 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 156774 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 36952841 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 0.924006 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.578400 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 24411645 66.06% 66.06% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 3911686 10.59% 76.65% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 2348900 6.36% 83.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 1966009 5.32% 88.32% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 2782600 7.53% 95.85% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 888012 2.40% 98.26% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 476049 1.29% 99.55% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 133134 0.36% 99.91% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 34806 0.09% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 36952841 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 16764 1.09% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 1407478 91.75% 92.84% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 109853 7.16% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 61419 0.18% 0.18% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 19283233 56.48% 56.65% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 25726 0.08% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 370 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 11342799 33.22% 89.95% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 3431088 10.05% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 34144653 # Type of FU issued
|
|
system.cpu2.iq.rate 0.386887 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 1534095 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.044929 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 106851627 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 39425823 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 27268218 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 6778 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 3706 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 3093 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 35613758 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 3571 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 205973 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 1568043 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 1874 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 9216 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 577978 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 5372164 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 352557 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 1187539 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 4864839 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 90375 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 32148379 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 60078 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 6484809 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 3835337 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 371219 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 30634 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 2404 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 9216 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 105461 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 87459 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 192920 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 33152533 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 11055310 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 992120 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 72670 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 14453415 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 3670278 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 3398105 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 0.375646 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 32735616 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 27271311 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 15591378 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 28369462 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 0.309007 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.549583 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 7280422 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 357100 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 167971 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 35765164 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 0.687670 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.714660 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 27144865 75.90% 75.90% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 4185503 11.70% 87.60% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 1252343 3.50% 91.10% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 650255 1.82% 92.92% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 570350 1.59% 94.51% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 312906 0.87% 95.39% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 397008 1.11% 96.50% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 289788 0.81% 97.31% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 962146 2.69% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 35765164 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 19883492 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 24594616 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 8174125 # Number of memory references committed
|
|
system.cpu2.commit.loads 4916766 # Number of loads committed
|
|
system.cpu2.commit.membars 94500 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 3146107 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 3055 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 21842455 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 293773 # Number of function calls committed.
|
|
system.cpu2.commit.bw_lim_events 962146 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.rob.rob_reads 66150526 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 64978873 # The number of ROB writes
|
|
system.cpu2.timesIdled 360296 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 51301918 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 3567267972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 19835003 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 24546127 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.committedInsts_total 19835003 # Number of Instructions Simulated
|
|
system.cpu2.cpi 4.449445 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 4.449445 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 0.224747 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.224747 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 153135451 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 29084509 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_reads 22287 # number of floating regfile reads
|
|
system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 8972562 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 241289 # number of misc regfile writes
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981130976648 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 981130976648 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981130976648 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 981130976648 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|