92f021cbbe
This patch introduces the ability of making the coherent crossbar the point of coherency. If so, the crossbar does not forward packets where a cache with ownership has already committed to responding, and also does not forward any coherency-related packets that are not intended for a downstream memory controller. Thus, invalidations and upgrades are turned around in the crossbar, and the memory controller only sees normal reads and writes. In addition this patch moves the express snoop promotion of a packet to the crossbar, thus allowing the downstream cache to check the express snoop flag (as it should) for bypassing any blocking, rather than relying on whether a cache is responding or not.
407 lines
13 KiB
C++
407 lines
13 KiB
C++
/*
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* Copyright (c) 2011-2013, 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Steve Reinhardt
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* Andreas Hansson
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*/
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/**
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* @file
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* Implementation of a memory-mapped bridge that connects a master
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* and a slave through a request and response queue.
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*/
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#include "base/trace.hh"
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#include "debug/Bridge.hh"
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#include "mem/bridge.hh"
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#include "params/Bridge.hh"
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Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
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Bridge& _bridge,
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BridgeMasterPort& _masterPort,
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Cycles _delay, int _resp_limit,
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std::vector<AddrRange> _ranges)
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: SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
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delay(_delay), ranges(_ranges.begin(), _ranges.end()),
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outstandingResponses(0), retryReq(false),
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respQueueLimit(_resp_limit), sendEvent(*this)
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{
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}
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Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
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Bridge& _bridge,
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BridgeSlavePort& _slavePort,
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Cycles _delay, int _req_limit)
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: MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
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delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
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{
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}
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Bridge::Bridge(Params *p)
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: MemObject(p),
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slavePort(p->name + ".slave", *this, masterPort,
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ticksToCycles(p->delay), p->resp_size, p->ranges),
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masterPort(p->name + ".master", *this, slavePort,
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ticksToCycles(p->delay), p->req_size)
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{
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}
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BaseMasterPort&
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Bridge::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "master")
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return masterPort;
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else
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// pass it along to our super class
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return MemObject::getMasterPort(if_name, idx);
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}
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BaseSlavePort&
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Bridge::getSlavePort(const std::string &if_name, PortID idx)
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{
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if (if_name == "slave")
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return slavePort;
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else
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// pass it along to our super class
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return MemObject::getSlavePort(if_name, idx);
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}
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void
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Bridge::init()
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{
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// make sure both sides are connected and have the same block size
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if (!slavePort.isConnected() || !masterPort.isConnected())
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fatal("Both ports of a bridge must be connected.\n");
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// notify the master side of our address ranges
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slavePort.sendRangeChange();
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}
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bool
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Bridge::BridgeSlavePort::respQueueFull() const
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{
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return outstandingResponses == respQueueLimit;
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}
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bool
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Bridge::BridgeMasterPort::reqQueueFull() const
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{
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return transmitList.size() == reqQueueLimit;
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}
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bool
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Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt)
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{
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// all checks are done when the request is accepted on the slave
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// side, so we are guaranteed to have space for the response
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DPRINTF(Bridge, "recvTimingResp: %s addr 0x%x\n",
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pkt->cmdString(), pkt->getAddr());
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DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size());
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// technically the packet only reaches us after the header delay,
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// and typically we also need to deserialise any payload (unless
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// the two sides of the bridge are synchronous)
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Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
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pkt->headerDelay = pkt->payloadDelay = 0;
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slavePort.schedTimingResp(pkt, bridge.clockEdge(delay) +
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receive_delay);
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return true;
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}
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bool
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Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt)
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{
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DPRINTF(Bridge, "recvTimingReq: %s addr 0x%x\n",
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pkt->cmdString(), pkt->getAddr());
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panic_if(pkt->cacheResponding(), "Should not see packets where cache "
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"is responding");
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// we should not get a new request after committing to retry the
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// current one, but unfortunately the CPU violates this rule, so
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// simply ignore it for now
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if (retryReq)
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return false;
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DPRINTF(Bridge, "Response queue size: %d outresp: %d\n",
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transmitList.size(), outstandingResponses);
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// if the request queue is full then there is no hope
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if (masterPort.reqQueueFull()) {
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DPRINTF(Bridge, "Request queue full\n");
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retryReq = true;
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} else {
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// look at the response queue if we expect to see a response
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bool expects_response = pkt->needsResponse();
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if (expects_response) {
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if (respQueueFull()) {
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DPRINTF(Bridge, "Response queue full\n");
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retryReq = true;
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} else {
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// ok to send the request with space for the response
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DPRINTF(Bridge, "Reserving space for response\n");
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assert(outstandingResponses != respQueueLimit);
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++outstandingResponses;
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// no need to set retryReq to false as this is already the
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// case
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}
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}
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if (!retryReq) {
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// technically the packet only reaches us after the header
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// delay, and typically we also need to deserialise any
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// payload (unless the two sides of the bridge are
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// synchronous)
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Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
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pkt->headerDelay = pkt->payloadDelay = 0;
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masterPort.schedTimingReq(pkt, bridge.clockEdge(delay) +
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receive_delay);
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}
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}
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// remember that we are now stalling a packet and that we have to
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// tell the sending master to retry once space becomes available,
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// we make no distinction whether the stalling is due to the
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// request queue or response queue being full
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return !retryReq;
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}
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void
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Bridge::BridgeSlavePort::retryStalledReq()
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{
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if (retryReq) {
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DPRINTF(Bridge, "Request waiting for retry, now retrying\n");
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retryReq = false;
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sendRetryReq();
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}
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}
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void
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Bridge::BridgeMasterPort::schedTimingReq(PacketPtr pkt, Tick when)
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{
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// If we're about to put this packet at the head of the queue, we
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// need to schedule an event to do the transmit. Otherwise there
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// should already be an event scheduled for sending the head
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// packet.
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if (transmitList.empty()) {
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bridge.schedule(sendEvent, when);
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}
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assert(transmitList.size() != reqQueueLimit);
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transmitList.emplace_back(pkt, when);
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}
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void
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Bridge::BridgeSlavePort::schedTimingResp(PacketPtr pkt, Tick when)
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{
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// If we're about to put this packet at the head of the queue, we
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// need to schedule an event to do the transmit. Otherwise there
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// should already be an event scheduled for sending the head
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// packet.
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if (transmitList.empty()) {
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bridge.schedule(sendEvent, when);
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}
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transmitList.emplace_back(pkt, when);
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}
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void
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Bridge::BridgeMasterPort::trySendTiming()
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{
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assert(!transmitList.empty());
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DeferredPacket req = transmitList.front();
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assert(req.tick <= curTick());
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PacketPtr pkt = req.pkt;
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DPRINTF(Bridge, "trySend request addr 0x%x, queue size %d\n",
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pkt->getAddr(), transmitList.size());
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if (sendTimingReq(pkt)) {
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// send successful
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transmitList.pop_front();
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DPRINTF(Bridge, "trySend request successful\n");
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// If there are more packets to send, schedule event to try again.
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if (!transmitList.empty()) {
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DeferredPacket next_req = transmitList.front();
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DPRINTF(Bridge, "Scheduling next send\n");
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bridge.schedule(sendEvent, std::max(next_req.tick,
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bridge.clockEdge()));
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}
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// if we have stalled a request due to a full request queue,
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// then send a retry at this point, also note that if the
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// request we stalled was waiting for the response queue
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// rather than the request queue we might stall it again
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slavePort.retryStalledReq();
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}
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// if the send failed, then we try again once we receive a retry,
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// and therefore there is no need to take any action
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}
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void
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Bridge::BridgeSlavePort::trySendTiming()
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{
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assert(!transmitList.empty());
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DeferredPacket resp = transmitList.front();
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assert(resp.tick <= curTick());
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PacketPtr pkt = resp.pkt;
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DPRINTF(Bridge, "trySend response addr 0x%x, outstanding %d\n",
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pkt->getAddr(), outstandingResponses);
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if (sendTimingResp(pkt)) {
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// send successful
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transmitList.pop_front();
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DPRINTF(Bridge, "trySend response successful\n");
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assert(outstandingResponses != 0);
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--outstandingResponses;
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// If there are more packets to send, schedule event to try again.
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if (!transmitList.empty()) {
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DeferredPacket next_resp = transmitList.front();
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DPRINTF(Bridge, "Scheduling next send\n");
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bridge.schedule(sendEvent, std::max(next_resp.tick,
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bridge.clockEdge()));
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}
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// if there is space in the request queue and we were stalling
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// a request, it will definitely be possible to accept it now
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// since there is guaranteed space in the response queue
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if (!masterPort.reqQueueFull() && retryReq) {
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DPRINTF(Bridge, "Request waiting for retry, now retrying\n");
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retryReq = false;
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sendRetryReq();
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}
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}
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// if the send failed, then we try again once we receive a retry,
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// and therefore there is no need to take any action
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}
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void
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Bridge::BridgeMasterPort::recvReqRetry()
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{
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trySendTiming();
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}
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void
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Bridge::BridgeSlavePort::recvRespRetry()
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{
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trySendTiming();
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}
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Tick
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Bridge::BridgeSlavePort::recvAtomic(PacketPtr pkt)
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{
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panic_if(pkt->cacheResponding(), "Should not see packets where cache "
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"is responding");
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return delay * bridge.clockPeriod() + masterPort.sendAtomic(pkt);
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}
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void
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Bridge::BridgeSlavePort::recvFunctional(PacketPtr pkt)
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{
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pkt->pushLabel(name());
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// check the response queue
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for (auto i = transmitList.begin(); i != transmitList.end(); ++i) {
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if (pkt->checkFunctional((*i).pkt)) {
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pkt->makeResponse();
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return;
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}
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}
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// also check the master port's request queue
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if (masterPort.checkFunctional(pkt)) {
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return;
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}
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pkt->popLabel();
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// fall through if pkt still not satisfied
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masterPort.sendFunctional(pkt);
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}
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bool
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Bridge::BridgeMasterPort::checkFunctional(PacketPtr pkt)
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{
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bool found = false;
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auto i = transmitList.begin();
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while (i != transmitList.end() && !found) {
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if (pkt->checkFunctional((*i).pkt)) {
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pkt->makeResponse();
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found = true;
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}
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++i;
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}
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return found;
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}
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AddrRangeList
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Bridge::BridgeSlavePort::getAddrRanges() const
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{
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return ranges;
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}
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Bridge *
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BridgeParams::create()
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{
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return new Bridge(this);
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}
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