gem5/src/mem/cache
Steve Reinhardt a25f3ac67f Forward cache-to-cache responses through other caches.
--HG--
extra : convert_revision : 5b6a02255bccd98b00949703cf4ba4b221553cea
2007-07-17 06:33:28 -07:00
..
miss Assert that an mshr has a target in getTarget(). 2007-07-17 06:23:11 -07:00
prefetch Getting closer... 2007-06-21 11:59:17 -07:00
tags Add CacheRepl trace flag and move a couple DPRINTFs to it. 2007-07-14 13:28:52 -07:00
base_cache.cc Fix up a few statistics problems. 2007-06-30 13:34:16 -07:00
base_cache.hh Move a couple of DPRINTFs from Cache to CachePort. 2007-07-14 13:16:58 -07:00
BaseCache.py Get rid of remaining traces of obsolete CoherenceProtocol object. 2007-06-30 17:59:45 -07:00
cache.cc Get rid of coherence protocol object. 2007-06-27 20:54:13 -07:00
cache.hh Get rid of coherence protocol object. 2007-06-27 20:54:13 -07:00
cache_blk.hh More major reorg of cache. Seems to work for atomic mode now, 2007-06-17 17:27:53 -07:00
cache_builder.cc Get rid of coherence protocol object. 2007-06-27 20:54:13 -07:00
cache_impl.hh Forward cache-to-cache responses through other caches. 2007-07-17 06:33:28 -07:00
SConscript Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00