sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

973 lines
111 KiB
Plaintext
Raw Blame History

---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
sim_ticks 19998000 # Number of ticks simulated
final_tick 19998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 99740 # Simulator instruction rate (inst/s)
host_op_rate 99716 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 344211505 # Simulator tick rate (ticks/s)
host_mem_usage 290580 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
system.physmem.bytes_read::total 28416 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
system.physmem.num_reads::total 444 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1097709771 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 323232323 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1420942094 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1097709771 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1097709771 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1097709771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 323232323 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1420942094 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 444 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 71 # Per bank write bursts
system.physmem.perBankRdBursts::1 42 # Per bank write bursts
system.physmem.perBankRdBursts::2 55 # Per bank write bursts
system.physmem.perBankRdBursts::3 58 # Per bank write bursts
system.physmem.perBankRdBursts::4 53 # Per bank write bursts
system.physmem.perBankRdBursts::5 61 # Per bank write bursts
system.physmem.perBankRdBursts::6 52 # Per bank write bursts
system.physmem.perBankRdBursts::7 10 # Per bank write bursts
system.physmem.perBankRdBursts::8 9 # Per bank write bursts
system.physmem.perBankRdBursts::9 28 # Per bank write bursts
system.physmem.perBankRdBursts::10 1 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdBursts::12 0 # Per bank write bursts
system.physmem.perBankRdBursts::13 0 # Per bank write bursts
system.physmem.perBankRdBursts::14 4 # Per bank write bursts
system.physmem.perBankRdBursts::15 0 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 19858500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 444 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 194.430832 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 340.544877 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 2.56% 84.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 3.85% 88.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation
system.physmem.totQLat 3950250 # Total ticks spent queuing
system.physmem.totMemAccLat 12275250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8896.96 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 27646.96 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1420.94 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1420.94 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 11.10 # Data bus utilization in percentage
system.physmem.busUtilRead 11.10 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 357 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 44726.35 # Average gap between requests
system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2519400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 15077640 # Total energy per rank (pJ)
system.physmem_0.averagePower 952.021468 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15318750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 7492365 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2927250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 11830500 # Total energy per rank (pJ)
system.physmem_1.averagePower 747.228802 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 6597250 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 10517250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 2331 # Number of BP lookups
system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups
system.cpu.branchPred.BTBHits 661 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.numCycles 39997 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 7837 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13501 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2331 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 4391 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12836 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.051807 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.461524 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10473 81.59% 81.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 190 1.48% 83.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 215 1.67% 84.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 153 1.19% 85.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 248 1.93% 87.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 135 1.05% 88.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 253 1.97% 90.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 115 0.90% 91.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1054 8.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12836 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.058279 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.337550 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 7233 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 3240 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1952 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 129 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 335 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 7391 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 953 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 624 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1916 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1670 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11195 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 1610 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 9626 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 18124 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 18098 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 4628 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 362 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2015 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4591 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3358 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 12836 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.709022 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.537942 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9696 75.54% 75.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 959 7.47% 83.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 638 4.97% 87.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 461 3.59% 91.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 440 3.43% 95.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 291 2.27% 97.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 236 1.84% 99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 68 0.53% 99.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 47 0.37% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12836 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 11 4.38% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 121 48.21% 52.59% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5531 60.77% 60.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.77% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1910 20.99% 81.78% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1658 18.22% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 9101 # Type of FU issued
system.cpu.iq.rate 0.227542 # Inst issue rate
system.cpu.iq.fu_busy_cnt 251 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.027579 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31302 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 14945 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8267 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9318 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1054 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 869 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2015 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8700 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3330 # number of memory reference insts executed
system.cpu.iew.exec_branches 1363 # Number of branches executed
system.cpu.iew.exec_stores 1554 # Number of stores executed
system.cpu.iew.exec_rate 0.217516 # Inst execution rate
system.cpu.iew.wb_sent 8425 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8294 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4459 # num instructions producing a value
system.cpu.iew.wb_consumers 7044 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.207366 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.633021 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 12125 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.477691 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.335541 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9949 82.05% 82.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 859 7.08% 89.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 524 4.32% 93.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 226 1.86% 95.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 182 1.50% 96.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 108 0.89% 97.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 109 0.90% 98.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 59 0.49% 99.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 109 0.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 12125 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2007 # Number of memory references committed
system.cpu.commit.loads 961 # Number of loads committed
system.cpu.commit.membars 7 # Number of memory barriers committed
system.cpu.commit.branches 1037 # Number of branches committed
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
system.cpu.commit.function_calls 103 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 22401 # The number of ROB reads
system.cpu.rob.rob_writes 21482 # The number of ROB writes
system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 27161 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 6.905559 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.905559 # CPI: Total CPI of All Threads
system.cpu.ipc 0.144811 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.144811 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 13740 # number of integer regfile reads
system.cpu.int_regfile_writes 7170 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 63.810933 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2272 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22.274510 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 63.810933 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.015579 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.015579 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1553 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1553 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2272 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2272 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2272 # number of overall hits
system.cpu.dcache.overall_hits::total 2272 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 441 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 441 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 441 # number of overall misses
system.cpu.dcache.overall_misses::total 441 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 32490996 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 32490996 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 41268496 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 41268496 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 41268496 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 41268496 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068386 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.068386 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.162551 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.162551 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.162551 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.162551 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76995.614035 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 76995.614035 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99360.844037 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 99360.844037 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 93579.356009 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 93579.356009 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 93579.356009 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 93579.356009 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 627 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.500000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4552000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4552000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4551498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4551498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9103498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9103498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9103498 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9103498 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82763.636364 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82763.636364 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96840.382979 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96840.382979 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89249.980392 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 89249.980392 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89249.980392 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 89249.980392 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 169.178952 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 169.178952 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.082607 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.082607 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4005 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits
system.cpu.icache.overall_hits::total 1389 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 439 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 439 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 439 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 439 # number of overall misses
system.cpu.icache.overall_misses::total 439 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31700000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 31700000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 31700000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 31700000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 31700000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 31700000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1828 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1828 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1828 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.240153 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.240153 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72209.567198 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 72209.567198 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72209.567198 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 72209.567198 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72209.567198 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 72209.567198 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 89 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 89 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 89 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 89 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26208500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 26208500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26208500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 26208500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26208500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 26208500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74881.428571 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74881.428571 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74881.428571 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 74881.428571 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74881.428571 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74881.428571 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 199.713481 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.994608 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.718873 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005127 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000968 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006095 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 7 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 344 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 344 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 54 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 54 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
system.cpu.l2cache.overall_misses::total 445 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4478000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4478000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25621500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25621500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4458500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4458500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 25621500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8936500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 34558000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 25621500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8936500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 34558000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.982857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981818 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981818 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95276.595745 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95276.595745 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74481.104651 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74481.104651 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82564.814815 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82564.814815 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77658.426966 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77658.426966 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 54 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 54 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4008000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4008000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22191500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22191500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3918500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3918500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22191500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7926500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 30118000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22191500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7926500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 30118000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981818 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85276.595745 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85276.595745 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64510.174419 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64510.174419 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72564.814815 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72564.814815 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.membus.trans_dist::ReadResp 397 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 444 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 444 # Request fanout histogram
system.membus.reqLayer0.occupancy 550500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 2342500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
Reference in a new issue View git blame Copy permalink