a5c4eb3de9
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems.
305 lines
9.6 KiB
C++
305 lines
9.6 KiB
C++
/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/interrupts.hh"
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#include "arch/x86/intmessage.hh"
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#include "cpu/base.hh"
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#include "debug/I82094AA.hh"
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#include "dev/x86/i82094aa.hh"
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#include "dev/x86/i8259.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/system.hh"
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X86ISA::I82094AA::I82094AA(Params *p)
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: BasicPioDevice(p, 20), IntDevice(this, p->int_latency),
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extIntPic(p->external_int_pic), lowestPriorityOffset(0)
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{
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// This assumes there's only one I/O APIC in the system and since the apic
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// id is stored in a 8-bit field with 0xff meaning broadcast, the id must
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// be less than 0xff
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assert(p->apic_id < 0xff);
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initialApicId = id = p->apic_id;
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arbId = id;
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regSel = 0;
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RedirTableEntry entry = 0;
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entry.mask = 1;
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for (int i = 0; i < TableSize; i++) {
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redirTable[i] = entry;
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pinStates[i] = false;
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}
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}
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void
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X86ISA::I82094AA::init()
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{
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// The io apic must register its address ranges on both its pio port
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// via the piodevice init() function and its int port that it inherited
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// from IntDevice. Note IntDevice is not a SimObject itself.
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BasicPioDevice::init();
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IntDevice::init();
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}
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BaseMasterPort &
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X86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "int_master")
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return intMasterPort;
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return BasicPioDevice::getMasterPort(if_name, idx);
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}
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AddrRangeList
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X86ISA::I82094AA::getIntAddrRange() const
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{
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AddrRangeList ranges;
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ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
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x86InterruptAddress(initialApicId, 0) +
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PhysAddrAPICRangeSize));
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return ranges;
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}
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Tick
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X86ISA::I82094AA::recvResponse(PacketPtr pkt)
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{
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// Packet instantiated calling sendMessage() in signalInterrupt()
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delete pkt->req;
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delete pkt;
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return 0;
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}
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Tick
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X86ISA::I82094AA::read(PacketPtr pkt)
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{
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assert(pkt->getSize() == 4);
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Addr offset = pkt->getAddr() - pioAddr;
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switch(offset) {
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case 0:
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pkt->set<uint32_t>(regSel);
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break;
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case 16:
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pkt->set<uint32_t>(readReg(regSel));
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break;
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default:
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panic("Illegal read from I/O APIC.\n");
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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X86ISA::I82094AA::write(PacketPtr pkt)
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{
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assert(pkt->getSize() == 4);
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Addr offset = pkt->getAddr() - pioAddr;
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switch(offset) {
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case 0:
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regSel = pkt->get<uint32_t>();
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break;
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case 16:
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writeReg(regSel, pkt->get<uint32_t>());
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break;
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default:
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panic("Illegal write to I/O APIC.\n");
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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void
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X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
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{
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if (offset == 0x0) {
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id = bits(value, 31, 24);
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} else if (offset == 0x1) {
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// The IOAPICVER register is read only.
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} else if (offset == 0x2) {
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arbId = bits(value, 31, 24);
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} else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
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int index = (offset - 0x10) / 2;
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if (offset % 2) {
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redirTable[index].topDW = value;
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redirTable[index].topReserved = 0;
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} else {
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redirTable[index].bottomDW = value;
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redirTable[index].bottomReserved = 0;
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}
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} else {
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warn("Access to undefined I/O APIC register %#x.\n", offset);
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}
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DPRINTF(I82094AA,
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"Wrote %#x to I/O APIC register %#x .\n", value, offset);
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}
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uint32_t
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X86ISA::I82094AA::readReg(uint8_t offset)
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{
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uint32_t result = 0;
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if (offset == 0x0) {
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result = id << 24;
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} else if (offset == 0x1) {
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result = ((TableSize - 1) << 16) | APICVersion;
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} else if (offset == 0x2) {
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result = arbId << 24;
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} else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
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int index = (offset - 0x10) / 2;
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if (offset % 2) {
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result = redirTable[index].topDW;
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} else {
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result = redirTable[index].bottomDW;
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}
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} else {
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warn("Access to undefined I/O APIC register %#x.\n", offset);
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}
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DPRINTF(I82094AA,
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"Read %#x from I/O APIC register %#x.\n", result, offset);
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return result;
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}
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void
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X86ISA::I82094AA::signalInterrupt(int line)
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{
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DPRINTF(I82094AA, "Received interrupt %d.\n", line);
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assert(line < TableSize);
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RedirTableEntry entry = redirTable[line];
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if (entry.mask) {
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DPRINTF(I82094AA, "Entry was masked.\n");
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return;
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} else {
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TriggerIntMessage message = 0;
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message.destination = entry.dest;
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if (entry.deliveryMode == DeliveryMode::ExtInt) {
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assert(extIntPic);
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message.vector = extIntPic->getVector();
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} else {
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message.vector = entry.vector;
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}
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message.deliveryMode = entry.deliveryMode;
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message.destMode = entry.destMode;
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message.level = entry.polarity;
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message.trigger = entry.trigger;
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ApicList apics;
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int numContexts = sys->numContexts();
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if (message.destMode == 0) {
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if (message.deliveryMode == DeliveryMode::LowestPriority) {
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panic("Lowest priority delivery mode from the "
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"IO APIC aren't supported in physical "
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"destination mode.\n");
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}
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if (message.destination == 0xFF) {
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for (int i = 0; i < numContexts; i++) {
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apics.push_back(i);
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}
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} else {
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apics.push_back(message.destination);
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}
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} else {
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for (int i = 0; i < numContexts; i++) {
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Interrupts *localApic = sys->getThreadContext(i)->
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getCpuPtr()->getInterruptController(0);
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if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
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message.destination) {
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apics.push_back(localApic->getInitialApicId());
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}
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}
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if (message.deliveryMode == DeliveryMode::LowestPriority &&
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apics.size()) {
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// The manual seems to suggest that the chipset just does
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// something reasonable for these instead of actually using
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// state from the local APIC. We'll just rotate an offset
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// through the set of APICs selected above.
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uint64_t modOffset = lowestPriorityOffset % apics.size();
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lowestPriorityOffset++;
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ApicList::iterator apicIt = apics.begin();
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while (modOffset--) {
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apicIt++;
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assert(apicIt != apics.end());
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}
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int selected = *apicIt;
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apics.clear();
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apics.push_back(selected);
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}
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}
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intMasterPort.sendMessage(apics, message, sys->isTimingMode());
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}
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}
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void
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X86ISA::I82094AA::raiseInterruptPin(int number)
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{
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assert(number < TableSize);
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if (!pinStates[number])
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signalInterrupt(number);
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pinStates[number] = true;
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}
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void
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X86ISA::I82094AA::lowerInterruptPin(int number)
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{
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assert(number < TableSize);
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pinStates[number] = false;
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}
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void
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X86ISA::I82094AA::serialize(CheckpointOut &cp) const
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{
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uint64_t* redirTableArray = (uint64_t*)redirTable;
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SERIALIZE_SCALAR(regSel);
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SERIALIZE_SCALAR(initialApicId);
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SERIALIZE_SCALAR(id);
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SERIALIZE_SCALAR(arbId);
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SERIALIZE_SCALAR(lowestPriorityOffset);
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SERIALIZE_ARRAY(redirTableArray, TableSize);
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SERIALIZE_ARRAY(pinStates, TableSize);
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}
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void
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X86ISA::I82094AA::unserialize(CheckpointIn &cp)
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{
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uint64_t redirTableArray[TableSize];
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UNSERIALIZE_SCALAR(regSel);
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UNSERIALIZE_SCALAR(initialApicId);
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UNSERIALIZE_SCALAR(id);
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UNSERIALIZE_SCALAR(arbId);
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UNSERIALIZE_SCALAR(lowestPriorityOffset);
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UNSERIALIZE_ARRAY(redirTableArray, TableSize);
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UNSERIALIZE_ARRAY(pinStates, TableSize);
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for (int i = 0; i < TableSize; i++) {
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redirTable[i] = (RedirTableEntry)redirTableArray[i];
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}
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}
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X86ISA::I82094AA *
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I82094AAParams::create()
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{
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return new X86ISA::I82094AA(this);
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}
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