a5802c823f
This changeset adds functionality that allows system calls to retry without affecting thread context state such as the program counter or register values for the associated thread context (when system calls return with a retry fault). This functionality is needed to solve problems with blocking system calls in multi-process or multi-threaded simulations where information is passed between processes/threads. Blocking system calls can cause deadlock because the simulator itself is single threaded. There is only a single thread servicing the event queue which can cause deadlock if the thread hits a blocking system call instruction. To illustrate the problem, consider two processes using the producer/consumer sharing model. The processes can use file descriptors and the read and write calls to pass information to one another. If the consumer calls the blocking read system call before the producer has produced anything, the call will block the event queue (while executing the system call instruction) and deadlock the simulation. The solution implemented in this changeset is to recognize that the system calls will block and then generate a special retry fault. The fault will be sent back up through the function call chain until it is exposed to the cpu model's pipeline where the fault becomes visible. The fault will trigger the cpu model to replay the instruction at a future tick where the call has a chance to succeed without actually going into a blocking state. In subsequent patches, we recognize that a syscall will block by calling a non-blocking poll (from inside the system call implementation) and checking for events. When events show up during the poll, it signifies that the call would not have blocked and the syscall is allowed to proceed (calling an underlying host system call if necessary). If no events are returned from the poll, we generate the fault and try the instruction for the thread context at a distant tick. Note that retrying every tick is not efficient. As an aside, the simulator has some multi-threading support for the event queue, but it is not used by default and needs work. Even if the event queue was completely multi-threaded, meaning that there is a hardware thread on the host servicing a single simulator thread contexts with a 1:1 mapping between them, it's still possible to run into deadlock due to the event queue barriers on quantum boundaries. The solution of replaying at a later tick is the simplest solution and solves the problem generally.
297 lines
10 KiB
C++
Executable file
297 lines
10 KiB
C++
Executable file
/*
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* Copyright (c) 2011-2012 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_THREAD_CONTEXT_HH__
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#define __CPU_O3_THREAD_CONTEXT_HH__
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#include "config/the_isa.hh"
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#include "cpu/o3/isa_specific.hh"
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#include "cpu/thread_context.hh"
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class EndQuiesceEvent;
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namespace Kernel {
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class Statistics;
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}
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/**
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* Derived ThreadContext class for use with the O3CPU. It
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* provides the interface for any external objects to access a
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* single thread's state and some general CPU state. Any time
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* external objects try to update state through this interface,
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* the CPU will create an event to squash all in-flight
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* instructions in order to ensure state is maintained correctly.
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* It must be defined specifically for the O3CPU because
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* not all architectural state is located within the O3ThreadState
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* (such as the commit PC, and registers), and specific actions
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* must be taken when using this interface (such as squashing all
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* in-flight instructions when doing a write to this interface).
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*/
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template <class Impl>
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class O3ThreadContext : public ThreadContext
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{
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public:
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typedef typename Impl::O3CPU O3CPU;
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/** Pointer to the CPU. */
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O3CPU *cpu;
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/** Pointer to the thread state that this TC corrseponds to. */
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O3ThreadState<Impl> *thread;
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/** Returns a pointer to the ITB. */
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TheISA::TLB *getITBPtr() { return cpu->itb; }
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/** Returns a pointer to the DTB. */
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TheISA::TLB *getDTBPtr() { return cpu->dtb; }
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CheckerCPU *getCheckerCpuPtr() { return NULL; }
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TheISA::Decoder *
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getDecoderPtr()
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{
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return cpu->fetch.decoder[thread->threadId()];
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}
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/** Returns a pointer to this CPU. */
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virtual BaseCPU *getCpuPtr() { return cpu; }
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/** Reads this CPU's ID. */
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virtual int cpuId() const { return cpu->cpuId(); }
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/** Reads this CPU's Socket ID. */
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virtual uint32_t socketId() const { return cpu->socketId(); }
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virtual ContextID contextId() const { return thread->contextId(); }
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virtual void setContextId(int id) { thread->setContextId(id); }
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/** Returns this thread's ID number. */
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virtual int threadId() const { return thread->threadId(); }
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virtual void setThreadId(int id) { return thread->setThreadId(id); }
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/** Returns a pointer to the system. */
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virtual System *getSystemPtr() { return cpu->system; }
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/** Returns a pointer to this thread's kernel statistics. */
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virtual TheISA::Kernel::Statistics *getKernelStats()
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{ return thread->kernelStats; }
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/** Returns a pointer to this thread's process. */
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virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
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virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
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virtual FSTranslatingPortProxy &getVirtProxy();
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virtual void initMemProxies(ThreadContext *tc)
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{ thread->initMemProxies(tc); }
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virtual SETranslatingPortProxy &getMemProxy()
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{ return thread->getMemProxy(); }
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/** Returns this thread's status. */
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virtual Status status() const { return thread->status(); }
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/** Sets this thread's status. */
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virtual void setStatus(Status new_status)
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{ thread->setStatus(new_status); }
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/** Set the status to Active. */
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virtual void activate();
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/** Set the status to Suspended. */
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virtual void suspend();
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/** Set the status to Halted. */
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virtual void halt();
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/** Dumps the function profiling information.
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* @todo: Implement.
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*/
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virtual void dumpFuncProfile();
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/** Takes over execution of a thread from another CPU. */
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virtual void takeOverFrom(ThreadContext *old_context);
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/** Registers statistics associated with this TC. */
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virtual void regStats(const std::string &name);
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/** Reads the last tick that this thread was activated on. */
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virtual Tick readLastActivate();
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/** Reads the last tick that this thread was suspended on. */
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virtual Tick readLastSuspend();
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/** Clears the function profiling information. */
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virtual void profileClear();
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/** Samples the function profiling information. */
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virtual void profileSample();
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/** Copies the architectural registers from another TC into this TC. */
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virtual void copyArchRegs(ThreadContext *tc);
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/** Resets all architectural registers to 0. */
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virtual void clearArchRegs();
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/** Reads an integer register. */
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virtual uint64_t readIntReg(int reg_idx) {
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return readIntRegFlat(flattenIntIndex(reg_idx));
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}
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virtual FloatReg readFloatReg(int reg_idx) {
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return readFloatRegFlat(flattenFloatIndex(reg_idx));
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}
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virtual FloatRegBits readFloatRegBits(int reg_idx) {
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return readFloatRegBitsFlat(flattenFloatIndex(reg_idx));
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}
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virtual CCReg readCCReg(int reg_idx) {
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return readCCRegFlat(flattenCCIndex(reg_idx));
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}
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/** Sets an integer register to a value. */
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virtual void setIntReg(int reg_idx, uint64_t val) {
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setIntRegFlat(flattenIntIndex(reg_idx), val);
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}
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virtual void setFloatReg(int reg_idx, FloatReg val) {
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setFloatRegFlat(flattenFloatIndex(reg_idx), val);
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}
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virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
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setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val);
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}
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virtual void setCCReg(int reg_idx, CCReg val) {
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setCCRegFlat(flattenCCIndex(reg_idx), val);
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}
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/** Reads this thread's PC state. */
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virtual TheISA::PCState pcState()
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{ return cpu->pcState(thread->threadId()); }
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/** Sets this thread's PC state. */
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virtual void pcState(const TheISA::PCState &val);
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virtual void pcStateNoRecord(const TheISA::PCState &val);
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/** Reads this thread's PC. */
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virtual Addr instAddr()
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{ return cpu->instAddr(thread->threadId()); }
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/** Reads this thread's next PC. */
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virtual Addr nextInstAddr()
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{ return cpu->nextInstAddr(thread->threadId()); }
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/** Reads this thread's next PC. */
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virtual MicroPC microPC()
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{ return cpu->microPC(thread->threadId()); }
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/** Reads a miscellaneous register. */
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virtual MiscReg readMiscRegNoEffect(int misc_reg) const
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{ return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
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/** Reads a misc. register, including any side-effects the
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* read might have as defined by the architecture. */
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virtual MiscReg readMiscReg(int misc_reg)
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{ return cpu->readMiscReg(misc_reg, thread->threadId()); }
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/** Sets a misc. register. */
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virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
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/** Sets a misc. register, including any side-effects the
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* write might have as defined by the architecture. */
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virtual void setMiscReg(int misc_reg, const MiscReg &val);
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virtual int flattenIntIndex(int reg);
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virtual int flattenFloatIndex(int reg);
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virtual int flattenCCIndex(int reg);
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virtual int flattenMiscIndex(int reg);
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/** Returns the number of consecutive store conditional failures. */
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// @todo: Figure out where these store cond failures should go.
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virtual unsigned readStCondFailures()
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{ return thread->storeCondFailures; }
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/** Sets the number of consecutive store conditional failures. */
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virtual void setStCondFailures(unsigned sc_failures)
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{ thread->storeCondFailures = sc_failures; }
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/** Executes a syscall in SE mode. */
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virtual void syscall(int64_t callnum, Fault *fault)
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{ return cpu->syscall(callnum, thread->threadId(), fault); }
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/** Reads the funcExeInst counter. */
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virtual Counter readFuncExeInst() { return thread->funcExeInst; }
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/** Returns pointer to the quiesce event. */
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virtual EndQuiesceEvent *getQuiesceEvent()
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{
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return this->thread->quiesceEvent;
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}
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/** check if the cpu is currently in state update mode and squash if not.
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* This function will return true if a trap is pending or if a fault or
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* similar is currently writing to the thread context and doesn't want
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* reset all the state (see noSquashFromTC).
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*/
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inline void conditionalSquash()
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{
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if (!thread->trapPending && !thread->noSquashFromTC)
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cpu->squashFromTC(thread->threadId());
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}
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virtual uint64_t readIntRegFlat(int idx);
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virtual void setIntRegFlat(int idx, uint64_t val);
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virtual FloatReg readFloatRegFlat(int idx);
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virtual void setFloatRegFlat(int idx, FloatReg val);
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virtual FloatRegBits readFloatRegBitsFlat(int idx);
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virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
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virtual CCReg readCCRegFlat(int idx);
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virtual void setCCRegFlat(int idx, CCReg val);
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};
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#endif
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