a5802c823f
This changeset adds functionality that allows system calls to retry without affecting thread context state such as the program counter or register values for the associated thread context (when system calls return with a retry fault). This functionality is needed to solve problems with blocking system calls in multi-process or multi-threaded simulations where information is passed between processes/threads. Blocking system calls can cause deadlock because the simulator itself is single threaded. There is only a single thread servicing the event queue which can cause deadlock if the thread hits a blocking system call instruction. To illustrate the problem, consider two processes using the producer/consumer sharing model. The processes can use file descriptors and the read and write calls to pass information to one another. If the consumer calls the blocking read system call before the producer has produced anything, the call will block the event queue (while executing the system call instruction) and deadlock the simulation. The solution implemented in this changeset is to recognize that the system calls will block and then generate a special retry fault. The fault will be sent back up through the function call chain until it is exposed to the cpu model's pipeline where the fault becomes visible. The fault will trigger the cpu model to replay the instruction at a future tick where the call has a chance to succeed without actually going into a blocking state. In subsequent patches, we recognize that a syscall will block by calling a non-blocking poll (from inside the system call implementation) and checking for events. When events show up during the poll, it signifies that the call would not have blocked and the syscall is allowed to proceed (calling an underlying host system call if necessary). If no events are returned from the poll, we generate the fault and try the instruction for the thread context at a distant tick. Note that retrying every tick is not efficient. As an aside, the simulator has some multi-threading support for the event queue, but it is not used by default and needs work. Even if the event queue was completely multi-threaded, meaning that there is a hardware thread on the host servicing a single simulator thread contexts with a 1:1 mapping between them, it's still possible to run into deadlock due to the event queue barriers on quantum boundaries. The solution of replaying at a later tick is the simplest solution and solves the problem generally.
262 lines
9 KiB
C++
262 lines
9 KiB
C++
/*
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* Copyright (c) 2010-2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_DYN_INST_IMPL_HH__
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#define __CPU_O3_DYN_INST_IMPL_HH__
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#include "base/cp_annotate.hh"
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#include "cpu/o3/dyn_inst.hh"
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#include "sim/full_system.hh"
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#include "debug/O3PipeView.hh"
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template <class Impl>
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BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &staticInst,
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const StaticInstPtr ¯oop,
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TheISA::PCState pc, TheISA::PCState predPC,
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InstSeqNum seq_num, O3CPU *cpu)
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: BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
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{
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initVars();
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}
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template <class Impl>
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BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &_staticInst,
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const StaticInstPtr &_macroop)
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: BaseDynInst<Impl>(_staticInst, _macroop)
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{
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initVars();
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}
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template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
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{
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#if TRACING_ON
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if (DTRACE(O3PipeView)) {
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Tick fetch = this->fetchTick;
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// fetchTick can be -1 if the instruction fetched outside the trace window.
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if (fetch != -1) {
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Tick val;
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// Print info needed by the pipeline activity viewer.
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DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
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fetch,
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this->instAddr(),
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this->microPC(),
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this->seqNum,
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this->staticInst->disassemble(this->instAddr()));
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val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
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DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
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val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
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DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
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val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
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DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
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val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
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DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
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val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
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DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
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val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
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Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
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DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS);
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}
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}
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#endif
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};
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template <class Impl>
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void
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BaseO3DynInst<Impl>::initVars()
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{
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// Make sure to have the renamed register entries set to the same
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// as the normal register entries. It will allow the IQ to work
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// without any modifications.
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for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
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this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
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}
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for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
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this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
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}
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this->_readySrcRegIdx.reset();
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_numDestMiscRegs = 0;
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#if TRACING_ON
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// Value -1 indicates that particular phase
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// hasn't happened (yet).
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fetchTick = -1;
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decodeTick = -1;
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renameTick = -1;
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dispatchTick = -1;
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issueTick = -1;
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completeTick = -1;
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commitTick = -1;
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storeTick = -1;
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#endif
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}
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template <class Impl>
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Fault
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BaseO3DynInst<Impl>::execute()
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{
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// @todo: Pretty convoluted way to avoid squashing from happening
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// when using the TC during an instruction's execution
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// (specifically for instructions that have side-effects that use
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// the TC). Fix this.
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bool no_squash_from_TC = this->thread->noSquashFromTC;
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this->thread->noSquashFromTC = true;
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this->fault = this->staticInst->execute(this, this->traceData);
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this->thread->noSquashFromTC = no_squash_from_TC;
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return this->fault;
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}
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template <class Impl>
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Fault
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BaseO3DynInst<Impl>::initiateAcc()
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{
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// @todo: Pretty convoluted way to avoid squashing from happening
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// when using the TC during an instruction's execution
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// (specifically for instructions that have side-effects that use
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// the TC). Fix this.
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bool no_squash_from_TC = this->thread->noSquashFromTC;
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this->thread->noSquashFromTC = true;
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this->fault = this->staticInst->initiateAcc(this, this->traceData);
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this->thread->noSquashFromTC = no_squash_from_TC;
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return this->fault;
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}
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template <class Impl>
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Fault
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BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
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{
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// @todo: Pretty convoluted way to avoid squashing from happening
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// when using the TC during an instruction's execution
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// (specifically for instructions that have side-effects that use
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// the TC). Fix this.
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bool no_squash_from_TC = this->thread->noSquashFromTC;
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this->thread->noSquashFromTC = true;
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if (this->cpu->checker) {
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if (this->isStoreConditional()) {
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this->reqToVerify->setExtraData(pkt->req->getExtraData());
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}
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}
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this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
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this->thread->noSquashFromTC = no_squash_from_TC;
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return this->fault;
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}
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template <class Impl>
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Fault
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BaseO3DynInst<Impl>::hwrei()
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{
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#if THE_ISA == ALPHA_ISA
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// Can only do a hwrei when in pal mode.
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if (!(this->instAddr() & 0x3))
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return std::make_shared<AlphaISA::UnimplementedOpcodeFault>();
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// Set the next PC based on the value of the EXC_ADDR IPR.
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AlphaISA::PCState pc = this->pcState();
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pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
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this->threadNumber));
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this->pcState(pc);
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if (CPA::available()) {
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ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
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CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
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}
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// Tell CPU to clear any state it needs to if a hwrei is taken.
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this->cpu->hwrei(this->threadNumber);
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#else
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#endif
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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}
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template <class Impl>
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void
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BaseO3DynInst<Impl>::trap(const Fault &fault)
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{
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this->cpu->trap(fault, this->threadNumber, this->staticInst);
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}
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template <class Impl>
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bool
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BaseO3DynInst<Impl>::simPalCheck(int palFunc)
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{
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#if THE_ISA != ALPHA_ISA
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panic("simPalCheck called, but PAL only exists in Alpha!\n");
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#endif
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return this->cpu->simPalCheck(palFunc, this->threadNumber);
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}
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template <class Impl>
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void
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BaseO3DynInst<Impl>::syscall(int64_t callnum, Fault *fault)
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{
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if (FullSystem)
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panic("Syscall emulation isn't available in FS mode.\n");
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// HACK: check CPU's nextPC before and after syscall. If it
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// changes, update this instruction's nextPC because the syscall
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// must have changed the nextPC.
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TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
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this->cpu->syscall(callnum, this->threadNumber, fault);
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TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
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if (!(curPC == newPC)) {
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this->pcState(newPC);
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}
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}
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#endif//__CPU_O3_DYN_INST_IMPL_HH__
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