a5802c823f
This changeset adds functionality that allows system calls to retry without affecting thread context state such as the program counter or register values for the associated thread context (when system calls return with a retry fault). This functionality is needed to solve problems with blocking system calls in multi-process or multi-threaded simulations where information is passed between processes/threads. Blocking system calls can cause deadlock because the simulator itself is single threaded. There is only a single thread servicing the event queue which can cause deadlock if the thread hits a blocking system call instruction. To illustrate the problem, consider two processes using the producer/consumer sharing model. The processes can use file descriptors and the read and write calls to pass information to one another. If the consumer calls the blocking read system call before the producer has produced anything, the call will block the event queue (while executing the system call instruction) and deadlock the simulation. The solution implemented in this changeset is to recognize that the system calls will block and then generate a special retry fault. The fault will be sent back up through the function call chain until it is exposed to the cpu model's pipeline where the fault becomes visible. The fault will trigger the cpu model to replay the instruction at a future tick where the call has a chance to succeed without actually going into a blocking state. In subsequent patches, we recognize that a syscall will block by calling a non-blocking poll (from inside the system call implementation) and checking for events. When events show up during the poll, it signifies that the call would not have blocked and the syscall is allowed to proceed (calling an underlying host system call if necessary). If no events are returned from the poll, we generate the fault and try the instruction for the thread context at a distant tick. Note that retrying every tick is not efficient. As an aside, the simulator has some multi-threading support for the event queue, but it is not used by default and needs work. Even if the event queue was completely multi-threaded, meaning that there is a hardware thread on the host servicing a single simulator thread contexts with a 1:1 mapping between them, it's still possible to run into deadlock due to the event queue barriers on quantum boundaries. The solution of replaying at a later tick is the simplest solution and solves the problem generally.
299 lines
9.5 KiB
C++
299 lines
9.5 KiB
C++
/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Andreas Sandberg
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*/
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#ifndef __CPU_EXEC_CONTEXT_HH__
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#define __CPU_EXEC_CONTEXT_HH__
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#include "arch/registers.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/static_inst_fwd.hh"
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#include "cpu/translation.hh"
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#include "mem/request.hh"
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/**
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* The ExecContext is an abstract base class the provides the
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* interface used by the ISA to manipulate the state of the CPU model.
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*
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* Register accessor methods in this class typically provide the index
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* of the instruction's operand (e.g., 0 or 1), not the architectural
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* register index, to simplify the implementation of register
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* renaming. The architectural register index can be found by
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* indexing into the instruction's own operand index table.
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*
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* @note The methods in this class typically take a raw pointer to the
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* StaticInst is provided instead of a ref-counted StaticInstPtr to
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* reduce overhead as an argument. This is fine as long as the
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* implementation doesn't copy the pointer into any long-term storage
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* (which is pretty hard to imagine they would have reason to do).
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*/
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class ExecContext {
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public:
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typedef TheISA::IntReg IntReg;
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typedef TheISA::PCState PCState;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::CCReg CCReg;
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public:
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/**
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* @{
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* @name Integer Register Interfaces
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*
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*/
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/** Reads an integer register. */
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virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
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/** Sets an integer register to a value. */
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virtual void setIntRegOperand(const StaticInst *si,
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int idx, IntReg val) = 0;
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/** @} */
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/**
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* @{
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* @name Floating Point Register Interfaces
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*/
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/** Reads a floating point register of single register width. */
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virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;
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/** Reads a floating point register in its binary format, instead
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* of by value. */
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virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
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int idx) = 0;
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/** Sets a floating point register of single width to a value. */
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virtual void setFloatRegOperand(const StaticInst *si,
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int idx, FloatReg val) = 0;
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/** Sets the bits of a floating point register of single width
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* to a binary value. */
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virtual void setFloatRegOperandBits(const StaticInst *si,
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int idx, FloatRegBits val) = 0;
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/** @} */
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/**
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* @{
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* @name Condition Code Registers
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*/
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virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
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virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
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/** @} */
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/**
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* @{
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* @name Misc Register Interfaces
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*/
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virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
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virtual void setMiscRegOperand(const StaticInst *si,
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int idx, const MiscReg &val) = 0;
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/**
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* Reads a miscellaneous register, handling any architectural
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* side effects due to reading that register.
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*/
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virtual MiscReg readMiscReg(int misc_reg) = 0;
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/**
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* Sets a miscellaneous register, handling any architectural
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* side effects due to writing that register.
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*/
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virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
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/** @} */
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/**
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* @{
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* @name PC Control
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*/
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virtual PCState pcState() const = 0;
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virtual void pcState(const PCState &val) = 0;
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/** @} */
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/**
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* @{
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* @name Memory Interface
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*/
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/**
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* Record the effective address of the instruction.
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*
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* @note Only valid for memory ops.
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*/
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virtual void setEA(Addr EA) = 0;
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/**
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* Get the effective address of the instruction.
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*
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* @note Only valid for memory ops.
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*/
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virtual Addr getEA() const = 0;
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/**
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* Perform an atomic memory read operation. Must be overridden
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* for exec contexts that support atomic memory mode. Not pure
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* virtual since exec contexts that only support timing memory
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* mode need not override (though in that case this function
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* should never be called).
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*/
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virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
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Request::Flags flags)
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{
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panic("ExecContext::readMem() should be overridden\n");
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}
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/**
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* Initiate a timing memory read operation. Must be overridden
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* for exec contexts that support timing memory mode. Not pure
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* virtual since exec contexts that only support atomic memory
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* mode need not override (though in that case this function
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* should never be called).
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*/
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virtual Fault initiateMemRead(Addr addr, unsigned int size,
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Request::Flags flags)
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{
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panic("ExecContext::initiateMemRead() should be overridden\n");
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}
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/**
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* For atomic-mode contexts, perform an atomic memory write operation.
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* For timing-mode contexts, initiate a timing memory write operation.
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*/
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virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
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Request::Flags flags, uint64_t *res) = 0;
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/**
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* Sets the number of consecutive store conditional failures.
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*/
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virtual void setStCondFailures(unsigned int sc_failures) = 0;
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/**
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* Returns the number of consecutive store conditional failures.
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*/
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virtual unsigned int readStCondFailures() const = 0;
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/** @} */
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/**
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* @{
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* @name SysCall Emulation Interfaces
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*/
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/**
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* Executes a syscall specified by the callnum.
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*/
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virtual void syscall(int64_t callnum, Fault *fault) = 0;
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/** @} */
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/** Returns a pointer to the ThreadContext. */
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virtual ThreadContext *tcBase() = 0;
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/**
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* @{
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* @name Alpha-Specific Interfaces
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*/
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/**
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* Somewhat Alpha-specific function that handles returning from an
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* error or interrupt.
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*/
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virtual Fault hwrei() = 0;
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/**
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* Check for special simulator handling of specific PAL calls. If
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* return value is false, actual PAL call will be suppressed.
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*/
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virtual bool simPalCheck(int palFunc) = 0;
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/** @} */
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/**
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* @{
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* @name ARM-Specific Interfaces
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*/
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virtual bool readPredicate() = 0;
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virtual void setPredicate(bool val) = 0;
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/** @} */
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/**
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* @{
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* @name X86-Specific Interfaces
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*/
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/**
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* Invalidate a page in the DTLB <i>and</i> ITLB.
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*/
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virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
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virtual void armMonitor(Addr address) = 0;
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virtual bool mwait(PacketPtr pkt) = 0;
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virtual void mwaitAtomic(ThreadContext *tc) = 0;
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virtual AddressMonitor *getAddrMonitor() = 0;
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/** @} */
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/**
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* @{
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* @name MIPS-Specific Interfaces
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*/
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#if THE_ISA == MIPS_ISA
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virtual MiscReg readRegOtherThread(int regIdx,
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ThreadID tid = InvalidThreadID) = 0;
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virtual void setRegOtherThread(int regIdx, MiscReg val,
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ThreadID tid = InvalidThreadID) = 0;
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#endif
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/** @} */
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};
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#endif // __CPU_EXEC_CONTEXT_HH__
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