0acd2a96e5
A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions.
281 lines
8.8 KiB
C++
281 lines
8.8 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Steve Reinhardt
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////////////////////////////////////////////////////////////////////
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//
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// Control transfer instructions
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//
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output header {{
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/**
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* Base class for instructions whose disassembly is not purely a
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* function of the machine instruction (i.e., it depends on the
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* PC). This class overrides the disassemble() method to check
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* the PC and symbol table values before re-using a cached
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* disassembly string. This is necessary for branches and jumps,
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* where the disassembly string includes the target address (which
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* may depend on the PC and/or symbol table).
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*/
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class PCDependentDisassembly : public AlphaStaticInst
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{
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protected:
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/// Cached program counter from last disassembly
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mutable Addr cachedPC;
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/// Cached symbol table pointer from last disassembly
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mutable const SymbolTable *cachedSymtab;
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/// Constructor
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PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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: AlphaStaticInst(mnem, _machInst, __opClass),
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cachedPC(0), cachedSymtab(0)
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{
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}
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const std::string &
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disassemble(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for branches (PC-relative control transfers),
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* conditional or unconditional.
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*/
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class Branch : public PCDependentDisassembly
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{
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protected:
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/// Displacement to target address (signed).
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int32_t disp;
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/// Constructor.
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Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(BRDISP << 2)
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{
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}
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AlphaISA::PCState branchTarget(const AlphaISA::PCState &branchPC) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for jumps (register-indirect control transfers). In
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* the Alpha ISA, these are always unconditional.
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*/
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class Jump : public PCDependentDisassembly
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{
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protected:
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/// Displacement to target address (signed).
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int32_t disp;
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public:
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/// Constructor
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Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(BRDISP)
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{
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}
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AlphaISA::PCState branchTarget(ThreadContext *tc) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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AlphaISA::PCState
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Branch::branchTarget(const AlphaISA::PCState &branchPC) const
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{
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return branchPC.pc() + 4 + disp;
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}
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AlphaISA::PCState
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Jump::branchTarget(ThreadContext *tc) const
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{
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PCState pc = tc->pcState();
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uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
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pc.set((Rb & ~3) | (pc.pc() & 1));
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return pc;
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}
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const std::string &
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PCDependentDisassembly::disassemble(Addr pc,
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const SymbolTable *symtab) const
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{
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if (!cachedDisassembly ||
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pc != cachedPC || symtab != cachedSymtab)
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{
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if (cachedDisassembly)
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delete cachedDisassembly;
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cachedDisassembly =
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new std::string(generateDisassembly(pc, symtab));
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cachedPC = pc;
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cachedSymtab = symtab;
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}
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return *cachedDisassembly;
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}
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std::string
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Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// There's only one register arg (RA), but it could be
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// either a source (the condition for conditional
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// branches) or a destination (the link reg for
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// unconditional branches)
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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ss << ",";
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}
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else if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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ss << ",";
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}
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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if (_numSrcRegs == 0 && _numDestRegs == 0) {
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printReg(ss, 31);
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ss << ",";
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}
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#endif
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Addr target = pc + 4 + disp;
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std::string str;
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if (symtab && symtab->findSymbol(target, str))
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ss << str;
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else
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ccprintf(ss, "0x%x", target);
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return ss.str();
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}
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std::string
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Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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if (_numDestRegs == 0) {
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printReg(ss, 31);
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ss << ",";
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}
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#endif
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if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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ss << ",";
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}
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ccprintf(ss, "(r%d)", RB);
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return ss.str();
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}
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}};
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def template JumpOrBranchDecode {{
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return (RA == 31)
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? (StaticInst *)new %(class_name)s(machInst)
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: (StaticInst *)new %(class_name)sAndLink(machInst);
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}};
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def format CondBranch(code) {{
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code = '''
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bool cond;
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%(code)s;
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if (cond)
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NPC = NPC + disp;
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else
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NPC = NPC;
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''' % { "code" : code }
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iop = InstObjParams(name, Name, 'Branch', code,
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('IsDirectControl', 'IsCondControl'))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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let {{
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def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
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# Declare basic control transfer w/o link (i.e. link reg is R31)
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nolink_code = 'NPC = %s;\n' % npc_expr
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nolink_iop = InstObjParams(name, Name, base_class,
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nolink_code, flags)
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header_output = BasicDeclare.subst(nolink_iop)
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decoder_output = BasicConstructor.subst(nolink_iop)
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exec_output = BasicExecute.subst(nolink_iop)
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# Generate declaration of '*AndLink' version, append to decls
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link_code = 'Ra = NPC & ~3;\n' + nolink_code
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link_iop = InstObjParams(name, Name + 'AndLink', base_class,
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link_code, flags)
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header_output += BasicDeclare.subst(link_iop)
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decoder_output += BasicConstructor.subst(link_iop)
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exec_output += BasicExecute.subst(link_iop)
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# need to use link_iop for the decode template since it is expecting
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# the shorter version of class_name (w/o "AndLink")
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return (header_output, decoder_output,
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JumpOrBranchDecode.subst(nolink_iop), exec_output)
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}};
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def format UncondBranch(*flags) {{
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flags += ('IsUncondControl', 'IsDirectControl')
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(header_output, decoder_output, decode_block, exec_output) = \
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UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
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}};
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def format Jump(*flags) {{
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flags += ('IsUncondControl', 'IsIndirectControl')
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(header_output, decoder_output, decode_block, exec_output) = \
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UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
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}};
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