a8b03e4d01
arch/alpha/isa/decoder.isa: Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model. arch/alpha/isa/pal.isa: Allow IPR instructions to have flags. base/traceflags.py: Include new trace flags from the two new CPU models. cpu/SConscript: Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next). cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Update to the BaseDynInst for the new models. --HG-- extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
189 lines
6.2 KiB
C++
189 lines
6.2 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_FREE_LIST_HH__
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#define __CPU_O3_FREE_LIST_HH__
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#include <iostream>
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#include <queue>
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#include "arch/isa_traits.hh"
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#include "base/trace.hh"
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#include "base/traceflags.hh"
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#include "cpu/o3/comm.hh"
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/**
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* FreeList class that simply holds the list of free integer and floating
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* point registers. Can request for a free register of either type, and
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* also send back free registers of either type. This is a very simple
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* class, but it should be sufficient for most implementations. Like all
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* other classes, it assumes that the indices for the floating point
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* registers starts after the integer registers end. Hence the variable
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* numPhysicalIntRegs is logically equivalent to the baseFP dependency.
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* Note that while this most likely should be called FreeList, the name
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* "FreeList" is used in a typedef within the CPU Policy, and therefore no
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* class can be named simply "FreeList".
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* @todo: Give a better name to the base FP dependency.
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*/
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class SimpleFreeList
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{
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private:
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/** The list of free integer registers. */
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std::queue<PhysRegIndex> freeIntRegs;
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/** The list of free floating point registers. */
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std::queue<PhysRegIndex> freeFloatRegs;
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/** Number of logical integer registers. */
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int numLogicalIntRegs;
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/** Number of physical integer registers. */
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int numPhysicalIntRegs;
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/** Number of logical floating point registers. */
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int numLogicalFloatRegs;
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/** Number of physical floating point registers. */
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int numPhysicalFloatRegs;
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/** Total number of physical registers. */
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int numPhysicalRegs;
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public:
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/** Constructs a free list.
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* @param activeThreads Number of active threads.
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* @param _numLogicalIntRegs Number of logical integer registers.
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* @param _numPhysicalIntRegs Number of physical integer registers.
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* @param _numLogicalFloatRegs Number of logical fp registers.
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* @param _numPhysicalFloatRegs Number of physical fp registers.
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*/
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SimpleFreeList(unsigned activeThreads,
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unsigned _numLogicalIntRegs,
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unsigned _numPhysicalIntRegs,
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unsigned _numLogicalFloatRegs,
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unsigned _numPhysicalFloatRegs);
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/** Gives the name of the freelist. */
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std::string name() const;
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/** Gets a free integer register. */
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inline PhysRegIndex getIntReg();
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/** Gets a free fp register. */
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inline PhysRegIndex getFloatReg();
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/** Adds a register back to the free list. */
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inline void addReg(PhysRegIndex freed_reg);
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/** Adds an integer register back to the free list. */
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inline void addIntReg(PhysRegIndex freed_reg);
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/** Adds a fp register back to the free list. */
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inline void addFloatReg(PhysRegIndex freed_reg);
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/** Checks if there are any free integer registers. */
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bool hasFreeIntRegs()
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{ return !freeIntRegs.empty(); }
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/** Checks if there are any free fp registers. */
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bool hasFreeFloatRegs()
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{ return !freeFloatRegs.empty(); }
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/** Returns the number of free integer registers. */
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int numFreeIntRegs()
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{ return freeIntRegs.size(); }
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/** Returns the number of free fp registers. */
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int numFreeFloatRegs()
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{ return freeFloatRegs.size(); }
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};
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inline PhysRegIndex
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SimpleFreeList::getIntReg()
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{
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DPRINTF(FreeList, "Trying to get free integer register.\n");
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if (freeIntRegs.empty()) {
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panic("No free integer registers!");
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}
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PhysRegIndex free_reg = freeIntRegs.front();
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freeIntRegs.pop();
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return(free_reg);
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}
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inline PhysRegIndex
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SimpleFreeList::getFloatReg()
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{
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DPRINTF(FreeList, "Trying to get free float register.\n");
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if (freeFloatRegs.empty()) {
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panic("No free integer registers!");
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}
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PhysRegIndex free_reg = freeFloatRegs.front();
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freeFloatRegs.pop();
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return(free_reg);
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}
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inline void
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SimpleFreeList::addReg(PhysRegIndex freed_reg)
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{
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DPRINTF(FreeList,"Freeing register %i.\n", freed_reg);
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//Might want to add in a check for whether or not this register is
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//already in there. A bit vector or something similar would be useful.
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if (freed_reg < numPhysicalIntRegs) {
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if (freed_reg != TheISA::ZeroReg)
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freeIntRegs.push(freed_reg);
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} else if (freed_reg < numPhysicalRegs) {
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if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs))
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freeFloatRegs.push(freed_reg);
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}
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}
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inline void
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SimpleFreeList::addIntReg(PhysRegIndex freed_reg)
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{
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DPRINTF(FreeList,"Freeing int register %i.\n", freed_reg);
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freeIntRegs.push(freed_reg);
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}
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inline void
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SimpleFreeList::addFloatReg(PhysRegIndex freed_reg)
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{
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DPRINTF(FreeList,"Freeing float register %i.\n", freed_reg);
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freeFloatRegs.push(freed_reg);
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}
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#endif // __CPU_O3_FREE_LIST_HH__
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