321 lines
8.3 KiB
C++
321 lines
8.3 KiB
C++
/* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#include "arch/arm/insts/static_inst.hh"
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#include "base/condcodes.hh"
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namespace ArmISA
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{
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// Shift Rm by an immediate value
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int32_t
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ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const
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{
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assert(shamt < 32);
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ArmShiftType shiftType;
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shiftType = (ArmShiftType)type;
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switch (shiftType)
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{
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case LSL:
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return base << shamt;
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case LSR:
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if (shamt == 0)
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return 0;
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else
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return base >> shamt;
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case ASR:
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if (shamt == 0)
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return (int32_t)base >> 31;
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else
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return (int32_t)base >> shamt;
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case ROR:
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if (shamt == 0)
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return (cfval << 31) | (base >> 1); // RRX
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else
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return (base << (32 - shamt)) | (base >> shamt);
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default:
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fprintf(stderr, "Unhandled shift type\n");
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exit(1);
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break;
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}
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return 0;
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}
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// Shift Rm by Rs
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int32_t
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ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const
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{
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enum ArmShiftType shiftType;
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shiftType = (enum ArmShiftType) type;
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switch (shiftType)
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{
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case LSL:
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if (shamt >= 32)
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return 0;
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else
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return base << shamt;
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case LSR:
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if (shamt >= 32)
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return 0;
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else
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return base >> shamt;
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case ASR:
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if (shamt >= 32)
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return (int32_t)base >> 31;
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else
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return (int32_t)base >> shamt;
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case ROR:
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shamt = shamt & 0x1f;
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if (shamt == 0)
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return base;
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else
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return (base << (32 - shamt)) | (base >> shamt);
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default:
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fprintf(stderr, "Unhandled shift type\n");
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exit(1);
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break;
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}
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return 0;
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}
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// Generate C for a shift by immediate
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bool
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ArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const
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{
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enum ArmShiftType shiftType;
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shiftType = (enum ArmShiftType) type;
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switch (shiftType)
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{
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case LSL:
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if (shamt == 0)
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return cfval;
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else
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return (base >> (32 - shamt)) & 1;
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case LSR:
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if (shamt == 0)
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return (base >> 31);
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else
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return (base >> (shamt - 1)) & 1;
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case ASR:
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if (shamt == 0)
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return (base >> 31);
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else
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return (base >> (shamt - 1)) & 1;
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case ROR:
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shamt = shamt & 0x1f;
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if (shamt == 0)
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return (base & 1); // RRX
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else
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return (base >> (shamt - 1)) & 1;
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default:
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fprintf(stderr, "Unhandled shift type\n");
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exit(1);
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break;
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}
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return 0;
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}
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// Generate C for a shift by Rs
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bool
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ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const
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{
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enum ArmShiftType shiftType;
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shiftType = (enum ArmShiftType) type;
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if (shamt == 0)
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return cfval;
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switch (shiftType)
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{
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case LSL:
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if (shamt > 32)
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return 0;
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else
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return (base >> (32 - shamt)) & 1;
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case LSR:
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if (shamt > 32)
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return 0;
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else
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return (base >> (shamt - 1)) & 1;
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case ASR:
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if (shamt > 32)
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shamt = 32;
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return (base >> (shamt - 1)) & 1;
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case ROR:
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shamt = shamt & 0x1f;
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if (shamt == 0)
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shamt = 32;
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return (base >> (shamt - 1)) & 1;
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default:
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fprintf(stderr, "Unhandled shift type\n");
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exit(1);
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break;
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}
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return 0;
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}
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// Generate the appropriate carry bit for an addition operation
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bool
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ArmStaticInst::arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const
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{
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return findCarry(32, result, lhs, rhs);
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}
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// Generate the appropriate carry bit for a subtraction operation
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bool
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ArmStaticInst::arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const
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{
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return findCarry(32, result, lhs, ~rhs);
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}
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bool
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ArmStaticInst::arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const
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{
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return findOverflow(32, result, lhs, rhs);
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}
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bool
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ArmStaticInst::arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const
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{
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return findOverflow(32, result, lhs, ~rhs);
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}
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void
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ArmStaticInst::printReg(std::ostream &os, int reg) const
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{
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if (reg < FP_Base_DepTag) {
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switch (reg) {
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case PCReg:
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ccprintf(os, "pc");
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break;
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case StackPointerReg:
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ccprintf(os, "sp");
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break;
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case FramePointerReg:
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ccprintf(os, "fp");
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break;
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case ReturnAddressReg:
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ccprintf(os, "lr");
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break;
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default:
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ccprintf(os, "r%d", reg);
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break;
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}
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} else if (reg < Ctrl_Base_DepTag) {
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ccprintf(os, "f%d", reg - FP_Base_DepTag);
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} else {
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reg -= Ctrl_Base_DepTag;
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assert(reg < NUM_MISCREGS);
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ccprintf(os, "%s", ArmISA::miscRegName[reg]);
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}
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}
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void
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ArmStaticInst::printMnemonic(std::ostream &os,
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const std::string &suffix,
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bool withPred) const
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{
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os << " " << mnemonic;
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if (withPred) {
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unsigned condCode = machInst.condCode;
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switch (condCode) {
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case COND_EQ:
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os << "eq";
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break;
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case COND_NE:
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os << "ne";
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break;
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case COND_CS:
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os << "cs";
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break;
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case COND_CC:
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os << "cc";
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break;
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case COND_MI:
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os << "mi";
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break;
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case COND_PL:
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os << "pl";
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break;
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case COND_VS:
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os << "vs";
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break;
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case COND_VC:
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os << "vc";
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break;
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case COND_HI:
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os << "hi";
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break;
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case COND_LS:
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os << "ls";
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break;
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case COND_GE:
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os << "ge";
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break;
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case COND_LT:
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os << "lt";
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break;
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case COND_GT:
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os << "gt";
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break;
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case COND_LE:
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os << "le";
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break;
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case COND_AL:
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// This one is implicit.
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break;
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case COND_NV:
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os << "nv";
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break;
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default:
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panic("Unrecognized condition code %d.\n", condCode);
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}
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os << suffix << " ";
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}
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}
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std::string
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ArmStaticInst::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss);
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return ss.str();
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}
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}
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