a48c24b61e
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
36 lines
1.2 KiB
Text
36 lines
1.2 KiB
Text
def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'shw' : ('signed int', 16),
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'uhw' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sd' : ('signed int', 64),
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'ud' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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'qf' : ('float', 128)
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}};
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def operands {{
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'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
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'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
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'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
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'R31': ('IntReg', 'uw','R31','IsInteger', 4),
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'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
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'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
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'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
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'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
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'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
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'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
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'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
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'NNPC': ('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
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#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
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#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
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# The next two are hacks for non-full-system call-pal emulation
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#'R0': ('IntReg', 'uq', '0', None, 1),
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}};
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