359 lines
12 KiB
C++
359 lines
12 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Andrew Schultz
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* Miguel Serrano
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*/
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/* @file
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* A single PCI device configuration space entry.
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*/
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#include <list>
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/intmath.hh"
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#include "base/misc.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "dev/alpha/tsunamireg.h"
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#include "dev/pciconfigall.hh"
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#include "dev/pcidev.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/byteswap.hh"
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#include "sim/core.hh"
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using namespace std;
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PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
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int funcid, Platform *p)
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: SimpleTimingPort(dev->name() + "-pciconf", dev), device(dev),
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platform(p), busId(busid), deviceId(devid), functionId(funcid)
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{
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configAddr = platform->calcPciConfigAddr(busId, deviceId, functionId);
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}
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Tick
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PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= configAddr &&
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pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
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return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
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}
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void
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PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp,
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bool &snoop)
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{
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snoop = false;;
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if (configAddr != ULL(-1))
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resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1));
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}
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PciDev::PciDev(const Params *p)
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: DmaDevice(p), plat(p->platform), pioDelay(p->pio_latency),
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configDelay(p->config_latency), configPort(NULL)
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{
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config.vendor = htole(p->VendorID);
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config.device = htole(p->DeviceID);
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config.command = htole(p->Command);
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config.status = htole(p->Status);
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config.revision = htole(p->Revision);
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config.progIF = htole(p->ProgIF);
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config.subClassCode = htole(p->SubClassCode);
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config.classCode = htole(p->ClassCode);
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config.cacheLineSize = htole(p->CacheLineSize);
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config.latencyTimer = htole(p->LatencyTimer);
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config.headerType = htole(p->HeaderType);
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config.bist = htole(p->BIST);
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config.baseAddr[0] = htole(p->BAR0);
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config.baseAddr[1] = htole(p->BAR1);
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config.baseAddr[2] = htole(p->BAR2);
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config.baseAddr[3] = htole(p->BAR3);
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config.baseAddr[4] = htole(p->BAR4);
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config.baseAddr[5] = htole(p->BAR5);
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config.cardbusCIS = htole(p->CardbusCIS);
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config.subsystemVendorID = htole(p->SubsystemVendorID);
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config.subsystemID = htole(p->SubsystemID);
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config.expansionROM = htole(p->ExpansionROM);
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config.reserved0 = 0;
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config.reserved1 = 0;
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config.interruptLine = htole(p->InterruptLine);
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config.interruptPin = htole(p->InterruptPin);
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config.minimumGrant = htole(p->MinimumGrant);
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config.maximumLatency = htole(p->MaximumLatency);
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BARSize[0] = p->BAR0Size;
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BARSize[1] = p->BAR1Size;
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BARSize[2] = p->BAR2Size;
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BARSize[3] = p->BAR3Size;
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BARSize[4] = p->BAR4Size;
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BARSize[5] = p->BAR5Size;
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legacyIO[0] = p->BAR0LegacyIO;
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legacyIO[1] = p->BAR1LegacyIO;
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legacyIO[2] = p->BAR2LegacyIO;
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legacyIO[3] = p->BAR3LegacyIO;
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legacyIO[4] = p->BAR4LegacyIO;
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legacyIO[5] = p->BAR5LegacyIO;
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for (int i = 0; i < 6; ++i) {
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if (legacyIO[i]) {
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BARAddrs[i] = platform->calcPciIOAddr(letoh(config.baseAddr[i]));
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config.baseAddr[i] = 0;
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} else {
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BARAddrs[i] = 0;
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uint32_t barsize = BARSize[i];
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if (barsize != 0 && !isPowerOf2(barsize)) {
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fatal("BAR %d size %d is not a power of 2\n", i, BARSize[i]);
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}
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}
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}
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plat->registerPciDevice(0, p->pci_dev, p->pci_func,
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letoh(config.interruptLine));
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}
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void
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PciDev::init()
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{
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if (!configPort)
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panic("pci config port not connected to anything!");
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configPort->sendStatusChange(Port::RangeChange);
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PioDevice::init();
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}
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unsigned int
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PciDev::drain(Event *de)
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{
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unsigned int count;
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count = pioPort->drain(de) + dmaPort->drain(de) + configPort->drain(de);
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if (count)
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changeState(Draining);
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else
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changeState(Drained);
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return count;
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}
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Tick
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PciDev::readConfig(PacketPtr pkt)
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{
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int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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if (offset >= PCI_DEVICE_SPECIFIC)
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panic("Device specific PCI config space not implemented!\n");
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pkt->allocate();
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switch (pkt->getSize()) {
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case sizeof(uint8_t):
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pkt->set<uint8_t>(config.data[offset]);
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DPRINTF(PCIDEV,
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"readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
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params()->pci_dev, params()->pci_func, offset,
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(uint32_t)pkt->get<uint8_t>());
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break;
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case sizeof(uint16_t):
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pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
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DPRINTF(PCIDEV,
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"readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
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params()->pci_dev, params()->pci_func, offset,
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(uint32_t)pkt->get<uint16_t>());
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break;
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case sizeof(uint32_t):
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pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
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DPRINTF(PCIDEV,
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"readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
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params()->pci_dev, params()->pci_func, offset,
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(uint32_t)pkt->get<uint32_t>());
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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pkt->makeAtomicResponse();
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return configDelay;
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}
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void
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PciDev::addressRanges(AddrRangeList &range_list)
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{
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int x = 0;
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range_list.clear();
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for (x = 0; x < 6; x++)
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if (BARAddrs[x] != 0)
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range_list.push_back(RangeSize(BARAddrs[x],BARSize[x]));
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}
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Tick
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PciDev::writeConfig(PacketPtr pkt)
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{
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int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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if (offset >= PCI_DEVICE_SPECIFIC)
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panic("Device specific PCI config space not implemented!\n");
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switch (pkt->getSize()) {
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case sizeof(uint8_t):
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switch (offset) {
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case PCI0_INTERRUPT_LINE:
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config.interruptLine = pkt->get<uint8_t>();
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break;
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case PCI_CACHE_LINE_SIZE:
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config.cacheLineSize = pkt->get<uint8_t>();
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break;
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case PCI_LATENCY_TIMER:
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config.latencyTimer = pkt->get<uint8_t>();
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break;
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/* Do nothing for these read-only registers */
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case PCI0_INTERRUPT_PIN:
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case PCI0_MINIMUM_GRANT:
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case PCI0_MAXIMUM_LATENCY:
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case PCI_CLASS_CODE:
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case PCI_REVISION_ID:
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break;
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default:
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panic("writing to a read only register");
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}
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DPRINTF(PCIDEV,
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"writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
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params()->pci_dev, params()->pci_func, offset,
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(uint32_t)pkt->get<uint8_t>());
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break;
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case sizeof(uint16_t):
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switch (offset) {
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case PCI_COMMAND:
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config.command = pkt->get<uint8_t>();
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break;
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case PCI_STATUS:
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config.status = pkt->get<uint8_t>();
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break;
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case PCI_CACHE_LINE_SIZE:
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config.cacheLineSize = pkt->get<uint8_t>();
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break;
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default:
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panic("writing to a read only register");
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}
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DPRINTF(PCIDEV,
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"writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
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params()->pci_dev, params()->pci_func, offset,
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(uint32_t)pkt->get<uint16_t>());
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break;
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case sizeof(uint32_t):
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switch (offset) {
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case PCI0_BASE_ADDR0:
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case PCI0_BASE_ADDR1:
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case PCI0_BASE_ADDR2:
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case PCI0_BASE_ADDR3:
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case PCI0_BASE_ADDR4:
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case PCI0_BASE_ADDR5:
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{
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int barnum = BAR_NUMBER(offset);
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if (!legacyIO[barnum]) {
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// convert BAR values to host endianness
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uint32_t he_old_bar = letoh(config.baseAddr[barnum]);
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uint32_t he_new_bar = letoh(pkt->get<uint32_t>());
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uint32_t bar_mask =
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BAR_IO_SPACE(he_old_bar) ? BAR_IO_MASK : BAR_MEM_MASK;
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// Writing 0xffffffff to a BAR tells the card to set the
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// value of the bar to a bitmask indicating the size of
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// memory it needs
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if (he_new_bar == 0xffffffff) {
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he_new_bar = ~(BARSize[barnum] - 1);
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} else {
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// does it mean something special to write 0 to a BAR?
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he_new_bar &= ~bar_mask;
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if (he_new_bar) {
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BARAddrs[barnum] = BAR_IO_SPACE(he_old_bar) ?
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platform->calcPciIOAddr(he_new_bar) :
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platform->calcPciMemAddr(he_new_bar);
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pioPort->sendStatusChange(Port::RangeChange);
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}
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}
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config.baseAddr[barnum] = htole((he_new_bar & ~bar_mask) |
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(he_old_bar & bar_mask));
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}
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}
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break;
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case PCI0_ROM_BASE_ADDR:
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if (letoh(pkt->get<uint32_t>()) == 0xfffffffe)
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config.expansionROM = htole((uint32_t)0xffffffff);
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else
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config.expansionROM = pkt->get<uint32_t>();
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break;
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case PCI_COMMAND:
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// This could also clear some of the error bits in the Status
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// register. However they should never get set, so lets ignore
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// it for now
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config.command = pkt->get<uint32_t>();
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break;
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default:
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DPRINTF(PCIDEV, "Writing to a read only register");
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}
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DPRINTF(PCIDEV,
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"writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
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params()->pci_dev, params()->pci_func, offset,
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(uint32_t)pkt->get<uint32_t>());
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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pkt->makeAtomicResponse();
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return configDelay;
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}
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void
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PciDev::serialize(ostream &os)
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{
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SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
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SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
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SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
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}
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void
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PciDev::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
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UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
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UNSERIALIZE_ARRAY(config.data,
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sizeof(config.data) / sizeof(config.data[0]));
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pioPort->sendStatusChange(Port::RangeChange);
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}
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