9023f5c96d
single place so it's easier to work with.
- Add support for binning kernel/user/idle time separately from
lisa's binning stuff, but make the two compatible.
- KernelStats used to directly implement the pImpl idiom, but
it makes more sense to just remove the level of indirection and
make the exec context have a pointer to the stats.
- Factor common code out of LinuxSystem and Tru64System and put
it into the System base class. While doing that, make all
constructors take a pointer to a parameter struct instead of
naming the parameters individually to make it much easier to add
parameters to these classes.
SConscript:
Move the function tracking and binning stuff around.
arch/alpha/ev5.cc:
kernelStats is now a pointer
arch/alpha/pseudo_inst.cc:
kernelStats is now a pointer
the parameters to the system have been moved into their own
struct
base/trace.hh:
provide a little functor class for wrapping a string that
can allow you to define name() in any scope very simply
for use with DPRINTF
cpu/base_cpu.cc:
New order of arguments for consistency.
cpu/exec_context.cc:
kernelStats no longer has the level of indirection in it,
execContext has the indirection now. so, kernelStats is a pointer.
We also need a pointer to the kernelBinning stuff from the system
and we need to figure out if we want to do binning or not.
Move a whole bunch of code into kern_binning.cc so it's all
in the same place.
cpu/exec_context.hh:
We want pointers to the kernel binning/stats stuff and we'll
have the exec_context and system have the level of indirection
instead of having the extra layer in the kernel stats class.
cpu/simple_cpu/simple_cpu.cc:
call through the exec context to do the special binning
stuff.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
Re-organize the stats stuff and remove the level of indirection
(that was there to simplify building) and move the binning stuff
into its own class/file.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/system.cc:
sim/system.hh:
move lots of common system code into the base system class so
that it can be shared between linux, tru64, and whatever else
we decide to support in the future.
Make the constructor take a pointer to a parameter struct so that
it is easier to pass parameters to the parent.
kern/system_events.cc:
move the majority of the binning code into the Kernel::Binning class
in the kern_binning file
kern/system_events.hh:
FnEvents only need to know the bin
create the Idle start event to find the PCBB of the idle
process when it starts.
kern/tru64/tru64_events.cc:
memCtrl -> memctrl
sim/process.cc:
sim/process.hh:
re-order args for consistency
--HG--
extra : convert_revision : 86cb39738c41fcd680f2aad125c9dde000227b2b
653 lines
17 KiB
C++
653 lines
17 KiB
C++
/* $Id$ */
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#include "arch/alpha/alpha_memory.hh"
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/osfpal.hh"
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#include "base/kgdb.h"
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#include "base/remote_gdb.hh"
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#include "base/stats/events.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/fast_cpu/fast_cpu.hh"
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#include "kern/kernel_stats.hh"
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#include "sim/debug.hh"
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#include "sim/sim_events.hh"
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#ifdef FULL_SYSTEM
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#ifndef SYSTEM_EV5
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#error This code is only valid for EV5 systems
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#endif
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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void
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AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
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{
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if (regs->pal_shadow == use_shadow)
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panic("swap_palshadow: wrong PAL shadow state");
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regs->pal_shadow = use_shadow;
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for (int i = 0; i < NumIntRegs; i++) {
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if (reg_redir[i]) {
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IntReg temp = regs->intRegFile[i];
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regs->intRegFile[i] = regs->palregs[i];
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regs->palregs[i] = temp;
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}
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}
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}
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////////////////////////////////////////////////////////////////////////
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//
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// Machine dependent functions
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//
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void
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AlphaISA::initCPU(RegFile *regs)
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{
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initIPRs(regs);
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// CPU comes up with PAL regs enabled
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swap_palshadow(regs, true);
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regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
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regs->npc = regs->pc + sizeof(MachInst);
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}
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////////////////////////////////////////////////////////////////////////
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//
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// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
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//
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Addr
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AlphaISA::fault_addr[Num_Faults] = {
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0x0000, /* No_Fault */
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0x0001, /* Reset_Fault */
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0x0401, /* Machine_Check_Fault */
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0x0501, /* Arithmetic_Fault */
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0x0101, /* Interrupt_Fault */
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0x0201, /* Ndtb_Miss_Fault */
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0x0281, /* Pdtb_Miss_Fault */
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0x0301, /* Alignment_Fault */
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0x0381, /* DTB_Fault_Fault */
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0x0381, /* DTB_Acv_Fault */
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0x0181, /* ITB_Miss_Fault */
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0x0181, /* ITB_Fault_Fault */
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0x0081, /* ITB_Acv_Fault */
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0x0481, /* Unimplemented_Opcode_Fault */
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0x0581, /* Fen_Fault */
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0x2001, /* Pal_Fault */
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0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
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};
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const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
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/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
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/* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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void
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AlphaISA::initIPRs(RegFile *regs)
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{
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uint64_t *ipr = regs->ipr;
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bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
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ipr[IPR_PAL_BASE] = PAL_BASE;
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ipr[IPR_MCSR] = 0x6;
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}
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template <class XC>
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void
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AlphaISA::processInterrupts(XC *xc)
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{
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//Check if there are any outstanding interrupts
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//Handle the interrupts
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int ipl = 0;
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int summary = 0;
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IntReg *ipr = xc->getIprPtr();
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check_interrupts = 0;
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if (ipr[IPR_ASTRR])
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panic("asynchronous traps not implemented\n");
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if (ipr[IPR_SIRR]) {
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for (int i = INTLEVEL_SOFTWARE_MIN;
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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if (ipr[IPR_SIRR] & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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}
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uint64_t interrupts = xc->intr_status();
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if (interrupts) {
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for (int i = INTLEVEL_EXTERNAL_MIN;
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i < INTLEVEL_EXTERNAL_MAX; i++) {
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if (interrupts & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = i;
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summary |= (ULL(1) << i);
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}
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}
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}
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if (ipl && ipl > ipr[IPR_IPLR]) {
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ipr[IPR_ISR] = summary;
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ipr[IPR_INTID] = ipl;
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xc->trap(Interrupt_Fault);
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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ipr[IPR_IPLR], ipl, summary);
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}
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}
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template <class XC>
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void
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AlphaISA::zeroRegisters(XC *xc)
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{
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// Insure ISA semantics
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// (no longer very clean due to the change in setIntReg() in the
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// cpu model. Consider changing later.)
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xc->xc->setIntReg(ZeroReg, 0);
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xc->xc->setFloatRegDouble(ZeroReg, 0.0);
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}
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void
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ExecContext::ev5_trap(Fault fault)
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{
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DPRINTF(Fault, "Fault %s\n", FaultName(fault));
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cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
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assert(!misspeculating());
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kernelStats->fault(fault);
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if (fault == Arithmetic_Fault)
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panic("Arithmetic traps are unimplemented!");
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AlphaISA::InternalProcReg *ipr = regs.ipr;
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// exception restart address
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if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
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ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
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if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
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fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
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// traps... skip faulting instruction
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ipr[AlphaISA::IPR_EXC_ADDR] += 4;
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}
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if (!PC_PAL(regs.pc))
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AlphaISA::swap_palshadow(®s, true);
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regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
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regs.npc = regs.pc + sizeof(MachInst);
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}
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void
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AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
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{
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InternalProcReg *ipr = regs->ipr;
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bool use_pc = (fault == No_Fault);
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if (fault == Arithmetic_Fault)
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panic("arithmetic faults NYI...");
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// compute exception restart address
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if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
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// traps... skip faulting instruction
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ipr[IPR_EXC_ADDR] = regs->pc + 4;
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} else {
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// fault, post fault at excepting instruction
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ipr[IPR_EXC_ADDR] = regs->pc;
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}
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// jump to expection address (PAL PC bit set here as well...)
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if (!use_pc)
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regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
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else
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regs->npc = ipr[IPR_PAL_BASE] + pc;
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// that's it! (orders of magnitude less painful than x86)
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}
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bool AlphaISA::check_interrupts = false;
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Fault
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ExecContext::hwrei()
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{
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uint64_t *ipr = regs.ipr;
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if (!PC_PAL(regs.pc))
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return Unimplemented_Opcode_Fault;
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setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
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if (!misspeculating()) {
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kernelStats->hwrei();
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if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
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AlphaISA::swap_palshadow(®s, false);
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AlphaISA::check_interrupts = true;
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}
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// FIXME: XXX check for interrupts? XXX
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return No_Fault;
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}
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uint64_t
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ExecContext::readIpr(int idx, Fault &fault)
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{
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uint64_t *ipr = regs.ipr;
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PALtemp23:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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case AlphaISA::IPR_ISR:
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case AlphaISA::IPR_EXC_ADDR:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_MCSR:
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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case AlphaISA::IPR_SIRR:
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case AlphaISA::IPR_ICSR:
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case AlphaISA::IPR_ICM:
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case AlphaISA::IPR_DTB_CM:
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case AlphaISA::IPR_IPLR:
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case AlphaISA::IPR_INTID:
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case AlphaISA::IPR_PMCTR:
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// no side-effect
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= curTick & ULL(0x00000000ffffffff);
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break;
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case AlphaISA::IPR_VA:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_VA_FORM:
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case AlphaISA::IPR_MM_STAT:
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case AlphaISA::IPR_IFAULT_VA_FORM:
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case AlphaISA::IPR_EXC_MASK:
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case AlphaISA::IPR_EXC_SUM:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_DTB_PTE:
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{
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AlphaISA::PTE &pte = dtb->index(!misspeculating());
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
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}
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break;
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// write only registers
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case AlphaISA::IPR_HWINT_CLR:
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case AlphaISA::IPR_SL_XMIT:
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case AlphaISA::IPR_DC_FLUSH:
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case AlphaISA::IPR_IC_FLUSH:
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case AlphaISA::IPR_ALT_MODE:
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case AlphaISA::IPR_DTB_IA:
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case AlphaISA::IPR_DTB_IAP:
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case AlphaISA::IPR_ITB_IA:
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case AlphaISA::IPR_ITB_IAP:
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fault = Unimplemented_Opcode_Fault;
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break;
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default:
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// invalid IPR
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fault = Unimplemented_Opcode_Fault;
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break;
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}
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return retval;
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}
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#ifdef DEBUG
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// Cause the simulator to break when changing to the following IPL
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int break_ipl = -1;
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#endif
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Fault
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ExecContext::setIpr(int idx, uint64_t val)
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{
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uint64_t *ipr = regs.ipr;
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uint64_t old;
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if (misspeculating())
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return No_Fault;
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_PMCTR:
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// write entire quad w/ no side-effect
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_CC_CTL:
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// This IPR resets the cycle counter. We assume this only
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// happens once... let's verify that.
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assert(ipr[idx] == 0);
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ipr[idx] = 1;
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break;
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case AlphaISA::IPR_CC:
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// This IPR only writes the upper 64 bits. It's ok to write
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// all 64 here since we mask out the lower 32 in rpcc (see
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// isa_desc).
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_PALtemp23:
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// write entire quad w/ no side-effect
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old = ipr[idx];
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ipr[idx] = val;
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kernelStats->context(old, val);
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break;
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case AlphaISA::IPR_DTB_PTE:
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// write entire quad w/ no side-effect, tag is forthcoming
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_EXC_ADDR:
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// second least significant bit in PC is always zero
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ipr[idx] = val & ~2;
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break;
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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// only write least significant four bits - privilege mask
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ipr[idx] = val & 0xf;
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break;
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case AlphaISA::IPR_IPLR:
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#ifdef DEBUG
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if (break_ipl != -1 && break_ipl == (val & 0x1f))
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debug_break();
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#endif
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// only write least significant five bits - interrupt level
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ipr[idx] = val & 0x1f;
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kernelStats->swpipl(ipr[idx]);
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break;
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case AlphaISA::IPR_DTB_CM:
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kernelStats->mode((val & 0x18) != 0);
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case AlphaISA::IPR_ICM:
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|
// only write two mode bits - processor mode
|
|
ipr[idx] = val & 0x18;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ALT_MODE:
|
|
// only write two mode bits - processor mode
|
|
ipr[idx] = val & 0x18;
|
|
break;
|
|
|
|
case AlphaISA::IPR_MCSR:
|
|
// more here after optimization...
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_SIRR:
|
|
// only write software interrupt mask
|
|
ipr[idx] = val & 0x7fff0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ICSR:
|
|
ipr[idx] = val & ULL(0xffffff0300);
|
|
break;
|
|
|
|
case AlphaISA::IPR_IVPTBR:
|
|
case AlphaISA::IPR_MVPTBR:
|
|
ipr[idx] = val & ULL(0xffffffffc0000000);
|
|
break;
|
|
|
|
case AlphaISA::IPR_DC_TEST_CTL:
|
|
ipr[idx] = val & 0x1ffb;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DC_MODE:
|
|
case AlphaISA::IPR_MAF_MODE:
|
|
ipr[idx] = val & 0x3f;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_ASN:
|
|
ipr[idx] = val & 0x7f0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_ASN:
|
|
ipr[idx] = val & ULL(0xfe00000000000000);
|
|
break;
|
|
|
|
case AlphaISA::IPR_EXC_SUM:
|
|
case AlphaISA::IPR_EXC_MASK:
|
|
// any write to this register clears it
|
|
ipr[idx] = 0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_INTID:
|
|
case AlphaISA::IPR_SL_RCV:
|
|
case AlphaISA::IPR_MM_STAT:
|
|
case AlphaISA::IPR_ITB_PTE_TEMP:
|
|
case AlphaISA::IPR_DTB_PTE_TEMP:
|
|
// read-only registers
|
|
return Unimplemented_Opcode_Fault;
|
|
|
|
case AlphaISA::IPR_HWINT_CLR:
|
|
case AlphaISA::IPR_SL_XMIT:
|
|
case AlphaISA::IPR_DC_FLUSH:
|
|
case AlphaISA::IPR_IC_FLUSH:
|
|
// the following are write only
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
dtb->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
dtb->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_TAG: {
|
|
struct AlphaISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
dtb->insert(val, pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_PTE: {
|
|
struct AlphaISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (ITB_PTE_GH(val) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = ITB_PTE_PPN(val);
|
|
pte.xre = ITB_PTE_XRE(val);
|
|
pte.xwe = 0;
|
|
pte.fonr = ITB_PTE_FONR(val);
|
|
pte.fonw = ITB_PTE_FONW(val);
|
|
pte.asma = ITB_PTE_ASMA(val);
|
|
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
itb->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
itb->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
|
break;
|
|
|
|
default:
|
|
// invalid IPR
|
|
return Unimplemented_Opcode_Fault;
|
|
}
|
|
|
|
// no error...
|
|
return No_Fault;
|
|
}
|
|
|
|
/**
|
|
* Check for special simulator handling of specific PAL calls.
|
|
* If return value is false, actual PAL call will be suppressed.
|
|
*/
|
|
bool
|
|
ExecContext::simPalCheck(int palFunc)
|
|
{
|
|
kernelStats->callpal(palFunc);
|
|
|
|
switch (palFunc) {
|
|
case PAL::halt:
|
|
halt();
|
|
if (--System::numSystemsRunning == 0)
|
|
new SimExitEvent("all cpus halted");
|
|
break;
|
|
|
|
case PAL::bpt:
|
|
case PAL::bugchk:
|
|
if (system->breakpoint())
|
|
return false;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
//Forward instantiation for FastCPU object
|
|
template
|
|
void AlphaISA::processInterrupts(FastCPU *xc);
|
|
|
|
//Forward instantiation for FastCPU object
|
|
template
|
|
void AlphaISA::zeroRegisters(FastCPU *xc);
|
|
|
|
#endif // FULL_SYSTEM
|