83f7e7afaf
This patch hosts gem5 onto SystemC scheduler. There's already an upstream
review board patch that does something similar but this patch ...:
1) is less obtrusive to the existing gem5 code organisation. It's divided
into the 'generic' preparatory patches (already submitted) and this patch
which affects no existing files
2) does not try to exactly track the gem5 event queue with notifys into
SystemC and so doesn't requive the event queue to be modified for
anything other than 'out of event queue' scheduling events
3) supports debug logging with SC_REPORT
The patch consists of the files:
util/systemc/
sc_gem5_control.{cc,hh} -- top level objects to use to
instantiate gem5 Systems within
larger SystemC test harnesses as
sc_module objects
sc_logger.{cc,hh} -- logging support
sc_module.{cc,hh} -- a separated event loop specific to
SystemC
stats.{cc,hh} -- example Stats handling for the sample
top level
main.{cc,hh} -- a sample top level
On the downside this patch is only currently functional with C++
configuration at the top level.
The above sc_... files are indended to be compiled alongside gem5 (as a
library, see main.cc for a command line and util/systemc/README for
more details.)
The top-level system instantiation in sc_gem5_control.{cc,hh} provides
two classes: Gem5Control and Gem5System
Gem5Control is a simulation control class (from which a singleton
object should be created) derived from Gem5SystemC::Module which
carries the top level simulation control interface for gem5. This
includes hosting a system-building configuration file and
instantiating the Root object from that file.
Gem5System is a base class for instantiating renamed gem5 Systems
from the config file hosted by the Gem5Control object. In use, a
SystemC module class should be made which represents the desired,
instantiable gem5 System. That class's instances should create
a Gem5System during their construction, set the parameters of that
system and then call instantiate to build that system. If this
is all carried out in the sc_core::sc_module-derived classes
constructor, the System's external ports will become children of
that module and can then be recovered by name using sc_core::
sc_find_object.
It is intended that this interface is used with dlopen. To that
end, the header file sc_gem5_control.hh includes no other header
files from gem5 (and so can be easily copied into another project).
The classes Gem5System and Gem5Control have all their member
functions declared `virtual' so that those functions can be called
through the vtable acquired by building the top level Gem5Control
using dlsym(..., "makeGem5Control") and `makeSystem' on the
Gem5Control.
115 lines
3.8 KiB
C++
115 lines
3.8 KiB
C++
/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andrew Bardsley
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*/
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/**
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* @file
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*
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* C++-only configuration stats handling example
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*
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* Register with: Stats::registerHandlers(statsReset, statsDump)
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*/
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#include "base/statistics.hh"
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#include "stats.hh"
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namespace CxxConfig
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{
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void statsPrepare()
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{
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std::list<Stats::Info *> stats = Stats::statsList();
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/* gather_stats -> prepare */
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for (auto i = stats.begin(); i != stats.end(); ++i)
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(*i)->prepare();
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}
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void statsDump()
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{
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std::cerr << "Stats dump\n";
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Stats::processDumpQueue();
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std::list<Stats::Info *> stats = Stats::statsList();
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statsPrepare();
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/* gather_stats -> convert_value */
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for (auto i = stats.begin(); i != stats.end(); ++i) {
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Stats::Info *stat = *i;
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Stats::ScalarInfo *scalar = dynamic_cast<Stats::ScalarInfo *>(stat);
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Stats::VectorInfo *vector = dynamic_cast<Stats::VectorInfo *>(stat);
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if (scalar) {
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std::cerr << "SCALAR " << stat->name << ' '
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<< scalar->value() << '\n';
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} else if (vector) {
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Stats::VResult results = vector->value();
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unsigned int index = 0;
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for (auto e = results.begin(); e != results.end(); ++e) {
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std::cerr << "VECTOR " << stat->name << '[' << index
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<< "] " << (*e) << '\n';
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index++;
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}
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std::cerr << "VTOTAL " << stat->name << ' '
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<< vector->total() << '\n';
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} else {
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std::cerr << "?????? " << stat->name << '\n';
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}
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}
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}
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void statsReset()
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{
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std::cerr << "Stats reset\n";
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Stats::processResetQueue();
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}
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void statsEnable()
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{
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std::list<Stats::Info *> stats = Stats::statsList();
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for (auto i = stats.begin(); i != stats.end(); ++i)
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(*i)->enable();
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}
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}
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