282 lines
31 KiB
Text
282 lines
31 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 23048 # Simulator instruction rate (inst/s)
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host_mem_usage 153228 # Number of bytes of host memory used
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host_seconds 0.28 # Real time elapsed on the host
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host_tick_rate 112412599 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 6404 # Number of instructions simulated
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sim_seconds 0.000031 # Number of seconds simulated
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sim_ticks 31286000 # Number of ticks simulated
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system.cpu.AGEN-Unit.instReqsProcessed 2050 # Number of Instructions Requests that completed in this resource.
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system.cpu.Branch-Predictor.instReqsProcessed 6581 # Number of Instructions Requests that completed in this resource.
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system.cpu.Branch-Predictor.predictedNotTaken 924 # Number of Branches Predicted As Not Taken (False).
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system.cpu.Branch-Predictor.predictedTaken 143 # Number of Branches Predicted As Taken (True).
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system.cpu.Decode-Unit.instReqsProcessed 6581 # Number of Instructions Requests that completed in this resource.
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system.cpu.Execution-Unit.cyclesExecuted 4340 # Number of Cycles Execution Unit was used.
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system.cpu.Execution-Unit.instReqsProcessed 4354 # Number of Instructions Requests that completed in this resource.
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system.cpu.Execution-Unit.predictedNotTakenIncorrect 608 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.Execution-Unit.predictedTakenIncorrect 123 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.Execution-Unit.utilization 0.069359 # Utilization of Execution Unit (cycles / totalCycles).
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system.cpu.Fetch-Seq-Unit.instReqsProcessed 13858 # Number of Instructions Requests that completed in this resource.
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system.cpu.Graduation-Unit.instReqsProcessed 6404 # Number of Instructions Requests that completed in this resource.
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system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed.
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system.cpu.Mult-Div-Unit.instReqsProcessed 2 # Number of Instructions Requests that completed in this resource.
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system.cpu.Mult-Div-Unit.multInstReqsProcessed 1 # Number of Multiply Requests Processed.
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system.cpu.RegFile-Manager.instReqsProcessed 19961 # Number of Instructions Requests that completed in this resource.
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system.cpu.activity 22.407428 # Percentage of cycles cpu is active
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system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread)
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system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total)
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.cpi 9.770924 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.cpi_total 9.770924 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 56347.368421 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53347.368421 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5353000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 5068000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56074.712644 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53074.712644 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 4878500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 4617500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 56217.032967 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53217.032967 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 10231500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 9685500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 56217.032967 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53217.032967 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 1868 # number of overall hits
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system.cpu.dcache.overall_miss_latency 10231500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 182 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 9685500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 103.689640 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dcache_port.instReqsProcessed 2050 # Number of Instructions Requests that completed in this resource.
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system.cpu.dtb.data_accesses 2060 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 2050 # DTB hits
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system.cpu.dtb.data_misses 10 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 1192 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 1185 # DTB read hits
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system.cpu.dtb.read_misses 7 # DTB read misses
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system.cpu.dtb.write_accesses 868 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 865 # DTB write hits
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system.cpu.dtb.write_misses 3 # DTB write misses
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system.cpu.icache.ReadReq_accesses 7277 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 55521.594684 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 52863.157895 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 6976 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 16712000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.041363 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 301 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 15066000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.039164 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 24.563380 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 7277 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 55521.594684 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency
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system.cpu.icache.demand_hits 6976 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 16712000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.041363 # miss rate for demand accesses
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system.cpu.icache.demand_misses 301 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 15066000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.039164 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 7277 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 55521.594684 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 6976 # number of overall hits
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system.cpu.icache.overall_miss_latency 16712000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.041363 # miss rate for overall accesses
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system.cpu.icache.overall_misses 301 # number of overall misses
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system.cpu.icache.overall_mshr_hits 16 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 15066000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.039164 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 130.373495 # Cycle average of tags in use
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system.cpu.icache.total_refs 6976 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache_port.instReqsProcessed 7275 # Number of Instructions Requests that completed in this resource.
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system.cpu.idleCycles 48552 # Number of cycles cpu's stages were not processed
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system.cpu.ipc 0.102344 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.ipc_total 0.102344 # IPC: Total IPC of All Threads
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.fetch_accesses 7294 # ITB accesses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_hits 7277 # ITB hits
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system.cpu.itb.fetch_misses 17 # ITB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52075.342466 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 3801500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52068.601583 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39945.910290 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 19734000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 15139500 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997368 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52071.428571 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 729000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.002747 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 453 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52069.690265 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 39956.858407 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 23535500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.997792 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 452 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 18060500 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.997792 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 452 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52069.690265 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 39956.858407 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 1 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 23535500 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.997792 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 452 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 18060500 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.997792 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 452 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 181.532273 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 62573 # number of cpu cycles simulated
|
|
system.cpu.runCycles 14021 # Number of cycles cpu stages are processed.
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
|
|
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
|
|
system.cpu.stage-0.idleCycles 55279 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-0.runCycles 7294 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-0.utilization 11.656785 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-1.idleCycles 55992 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-1.runCycles 6581 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-1.utilization 10.517316 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-2.idleCycles 56103 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-2.utilization 10.339923 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-3.idleCycles 60520 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-3.utilization 3.280968 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-4.idleCycles 56169 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-4.utilization 10.234446 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.threadCycles 62573 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|