bfd820f704
update miscReg file access
arch/mips/isa/decoder.isa:
arch/mips/isa_traits.cc:
update miscRegfile access
arch/mips/isa_traits.hh:
Update MiscReg enum and miscRegFile definition
--HG--
extra : convert_revision : 9b6b9343d674e1e38e25bb9a4ffe4325142e7424
403 lines
13 KiB
C++
403 lines
13 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/mips/isa_traits.hh"
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#include "config/full_system.hh"
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#include "cpu/static_inst.hh"
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#include "sim/serialize.hh"
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using namespace MipsISA;
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//Function now Obsolete in current state.
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//If anyting this should return the correct miscreg index
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//but that is handled implicitly with enums anyway
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void
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MipsISA::getMiscRegIdx(int reg_name,int &idx, int &sel)
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{
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switch(reg_name)
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{
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case Index: idx = 0; sel = 0; break; //0-0 Index into the TLB array
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case MVPControl: idx = 0; sel = 1; break; //0-1 Per-processor register containing global
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case MVPConf0: idx = 0; sel = 2; break; //0-2 Per-processor register containing global
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case MVPConf1: idx = 0; sel = 3; break; //0-3 Per-processor register containing global
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case Random: idx = 1; sel = 3; break; //1-0 Randomly generated index into the TLB array
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case VPEControl: idx = 1; sel = 1; break; //1-1 Per-VPE register containing relatively volatile
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//thread configuration data
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case VPEConf0: idx = 1; sel = 2; break; //1-2 Per-VPE multi-thread configuration
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//information
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case VPEConf1: idx = 1; sel = 3; break; //1-3 Per-VPE multi-thread configuration
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//information
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case YQMask: idx = 1; sel = 4; break; //Per-VPE register defining which YIELD
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//qualifier bits may be used without generating
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//an exception
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case VPESchedule: idx = 1; sel = 5; break;
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case VPEScheFBack: idx = 1; sel = 6; break;
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case VPEOpt: idx = 1; sel = 7; break;
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case EntryLo0: idx = 1; sel = 5; break;
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case TCStatus: idx = 1; sel = 5; break;
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case TCBind: idx = 1; sel = 5; break;
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case TCRestart: idx = 1; sel = 5; break;
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case TCHalt: idx = 1; sel = 5; break;
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case TCContext: idx = 1; sel = 5; break;
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case TCSchedule: idx = 1; sel = 5; break;
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case TCScheFBack: panic("Accessing Unimplemented CP0 Register"); break;
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case EntryLo1: panic("Accessing Unimplemented CP0 Register"); break;
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case Context: panic("Accessing Unimplemented CP0 Register"); break;
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case ContextConfig: panic("Accessing Unimplemented CP0 Register"); break;
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//case PageMask: panic("Accessing Unimplemented CP0 Register"); break;
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case PageGrain: panic("Accessing Unimplemented CP0 Register"); break;
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case Wired: panic("Accessing Unimplemented CP0 Register"); break;
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case SRSConf0: panic("Accessing Unimplemented CP0 Register"); break;
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case SRSConf1: panic("Accessing Unimplemented CP0 Register"); break;
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case SRSConf2: panic("Accessing Unimplemented CP0 Register"); break;
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case SRSConf3: panic("Accessing Unimplemented CP0 Register"); break;
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case SRSConf4: panic("Accessing Unimplemented CP0 Register"); break;
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case BadVAddr: panic("Accessing Unimplemented CP0 Register"); break;
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case Count: panic("Accessing Unimplemented CP0 Register"); break;
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case EntryHi: panic("Accessing Unimplemented CP0 Register"); break;
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case Compare: panic("Accessing Unimplemented CP0 Register"); break;
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case Status: idx = 12; sel = 0; break; //12-0 Processor status and control
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case IntCtl: idx = 12; sel = 1; break; //12-1 Interrupt system status and control
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case SRSCtl: idx = 12; sel = 2; break; //12-2 Shadow register set status and control
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case SRSMap: idx = 12; sel = 3; break; //12-3 Shadow set IPL mapping
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case Cause: idx = 13; sel = 0; break; //13-0 Cause of last general exception
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case EPC: idx = 14; sel = 0; break; //14-0 Program counter at last exception
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case PrId: idx = 15; sel = 0; break; //15-0 Processor identification and revision
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case EBase: idx = 15; sel = 1; break; //15-1 Exception vector base register
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case Config: panic("Accessing Unimplemented CP0 Register"); break;
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case Config1: panic("Accessing Unimplemented CP0 Register"); break;
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case Config2: panic("Accessing Unimplemented CP0 Register"); break;
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case Config3: panic("Accessing Unimplemented CP0 Register"); break;
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case LLAddr: panic("Accessing Unimplemented CP0 Register"); break;
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case WatchLo: panic("Accessing Unimplemented CP0 Register"); break;
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case WatchHi: panic("Accessing Unimplemented CP0 Register"); break;
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case Debug: panic("Accessing Unimplemented CP0 Register"); break;
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case TraceControl1: panic("Accessing Unimplemented CP0 Register"); break;
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case TraceControl2: panic("Accessing Unimplemented CP0 Register"); break;
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case UserTraceData: panic("Accessing Unimplemented CP0 Register"); break;
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case TraceBPC: panic("Accessing Unimplemented CP0 Register"); break;
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case DEPC: panic("Accessing Unimplemented CP0 Register"); break;
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case PerfCnt: panic("Accessing Unimplemented CP0 Register"); break;
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case ErrCtl: panic("Accessing Unimplemented CP0 Register"); break;
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case CacheErr0: panic("Accessing Unimplemented CP0 Register"); break;
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case CacheErr1: panic("Accessing Unimplemented CP0 Register"); break;
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case CacheErr2: panic("Accessing Unimplemented CP0 Register"); break;
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case CacheErr3: panic("Accessing Unimplemented CP0 Register"); break;
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case TagLo: panic("Accessing Unimplemented CP0 Register"); break;
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case DataLo: panic("Accessing Unimplemented CP0 Register"); break;
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case TagHi: panic("Accessing Unimplemented CP0 Register"); break;
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case DataHi: panic("Accessing Unimplemented CP0 Register"); break;
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case ErrorEPC: panic("Accessing Unimplemented CP0 Register"); break;
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default:
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panic("Accessing Unimplemented Misc. Register");
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}
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}
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void RegFile::coldReset()
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{
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//CP0 Random Reg:
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//Randomly generated index into the TLB array
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miscRegs[Random] = 0x0000003f;
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//CP0 Wired Reg.
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miscRegs[Wired] = 0x0000000;
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//CP0 HWRENA
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miscRegs[HWRena] = 0x0000000;
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//CP0 Status Reg.
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miscRegs[Status] = 0x0400004;
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//CP0 INTCNTL
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miscRegs[IntCtl] = 0xfc00000;
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//CP0 SRSCNTL
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miscRegs[SRSCtl] = 0x0c00000;
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//CP0 SRSMAP
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miscRegs[SRSMap] = 0x0000000;
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//CP0 Cause
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miscRegs[Cause] = 0x0000000;
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//CP0 Processor ID
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miscRegs[PrId] = 0x0019300;
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//CP0 EBASE
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miscRegs[EBase] = 0x8000000;
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//CP0 Config Reg.
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miscRegs[Config] = 0x80040482;
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//CP0 Config 1 Reg.
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miscRegs[Config1] = 0xfee3719e;
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//CP0 Config 2 Reg.
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miscRegs[Config2] = 0x8000000;
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//CP0 Config 3 Reg.
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miscRegs[Config3] = 0x0000020;
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//CP0 Config 7 Reg.
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miscRegs[Config7] = 0x0000000;
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//CP0 Debug
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miscRegs[Debug] = 0x0201800;
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//CP0 PERFCNTL1
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miscRegs[PerfCnt0] = 0x0000000;
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//CP0 PERFCNTL2
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miscRegs[PerfCnt1] = 0x0000000;
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}
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void RegFile::createCP0Regs()
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{
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//Resize Coprocessor Register Banks to
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// the number specified in MIPS32K VOL.III
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// Chapter 8
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/*
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//Cop-0 Regs. Bank 0: Index,
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miscRegs[0].resize(4);
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//Cop-0 Regs. Bank 1:
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miscRegs[1].resize(8);
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//Cop-0 Regs. Bank 2:
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miscRegs[2].resize(8);
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//Cop-0 Regs. Bank 3:
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miscRegs[3].resize(1);
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//Cop-0 Regs. Bank 4:
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miscRegs[4].resize(2);
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//Cop-0 Regs. Bank 5:
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miscRegs[5].resize(2);
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//Cop-0 Regs. Bank 6:
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miscRegs[6].resize(6);
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//Cop-0 Regs. Bank 7:
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miscRegs[7].resize(1);
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//Cop-0 Regs. Bank 8:
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miscRegs[8].resize(1);
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//Cop-0 Regs. Bank 9:
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miscRegs[9].resize(1);
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//Cop-0 Regs. Bank 10:
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miscRegs[10].resize(1);
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//Cop-0 Regs. Bank 11:
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miscRegs[11].resize(1);
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//Cop-0 Regs. Bank 12:
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miscRegs[12].resize(4);
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//Cop-0 Regs. Bank 13:
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miscRegs[13].resize(1);
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//Cop-0 Regs. Bank 14:
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miscRegs[14].resize(1);
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//Cop-0 Regs. Bank 15:
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miscRegs[15].resize(2);
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//Cop-0 Regs. Bank 16:
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miscRegs[16].resize(4);
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//Cop-0 Regs. Bank 17:
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miscRegs[17].resize(1);
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//Cop-0 Regs. Bank 18:
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miscRegs[18].resize(8);
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//Cop-0 Regs. Bank 19:
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miscRegs[19].resize(8);
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//Cop-0 Regs. Bank 20:
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miscRegs[20].resize(1);
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//Cop-0 Regs. Bank 21:
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//miscRegs[21].resize(1);
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//Reserved for future extensions
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//Cop-0 Regs. Bank 22:
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//miscRegs[22].resize(4);
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//Available for implementation dependent use
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//Cop-0 Regs. Bank 23:
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miscRegs[23].resize(5);
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//Cop-0 Regs. Bank 24:
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miscRegs[24].resize(1);
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//Cop-0 Regs. Bank 25:
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miscRegs[25].resize(8);
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//Cop-0 Regs. Bank 26:
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miscRegs[26].resize(1);
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//Cop-0 Regs. Bank 27:
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miscRegs[27].resize(4);
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//Cop-0 Regs. Bank 28:
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miscRegs[28].resize(8);
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//Cop-0 Regs. Bank 29:
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miscRegs[29].resize(8);
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//Cop-0 Regs. Bank 30:
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miscRegs[30].resize(1);
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//Cop-0 Regs. Bank 31:
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miscRegs[31].resize(1);*/
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}
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const Addr MipsISA::PageShift = 13;
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const Addr MipsISA::PageBytes = ULL(1) << PageShift;
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const Addr MipsISA::PageMask = ~(PageBytes - 1);
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const Addr MipsISA::PageOffset = PageBytes - 1;
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#if FULL_SYSTEM
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////////////////////////////////////////////////////////////////////////
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//
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// Translation stuff
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//
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const Addr MipsISA::PteShift = 3;
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const Addr MipsISA::NPtePageShift = PageShift - PteShift;
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const Addr MipsISA::NPtePage = ULL(1) << NPtePageShift;
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const Addr MipsISA::PteMask = NPtePage - 1;
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// User Virtual
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const Addr MipsISA::USegBase = ULL(0x0);
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const Addr MipsISA::USegEnd = ULL(0x000003ffffffffff);
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// Kernel Direct Mapped
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const Addr MipsISA::K0SegBase = ULL(0xfffffc0000000000);
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const Addr MipsISA::K0SegEnd = ULL(0xfffffdffffffffff);
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// Kernel Virtual
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const Addr MipsISA::K1SegBase = ULL(0xfffffe0000000000);
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const Addr MipsISA::K1SegEnd = ULL(0xffffffffffffffff);
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#endif
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// Mips UNOP (sll r0,r0,r0)
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const MachInst MipsISA::NoopMachInst = 0x00000000;
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static inline Addr
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TruncPage(Addr addr)
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{ return addr & ~(MipsISA::PageBytes - 1); }
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static inline Addr
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RoundPage(Addr addr)
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{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); }
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void
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RegFile::serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(intRegFile, NumIntRegs);
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SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
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//SERIALIZE_SCALAR(miscRegs.fpcr);
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//SERIALIZE_SCALAR(miscRegs.uniq);
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//SERIALIZE_SCALAR(miscRegs.lock_flag);
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//SERIALIZE_SCALAR(miscRegs.lock_addr);
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(npc);
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SERIALIZE_SCALAR(nnpc);
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#if FULL_SYSTEM
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SERIALIZE_ARRAY(palregs, NumIntRegs);
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SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
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SERIALIZE_SCALAR(intrflag);
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SERIALIZE_SCALAR(pal_shadow);
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#endif
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}
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void
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RegFile::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(intRegFile, NumIntRegs);
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UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
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//UNSERIALIZE_SCALAR(miscRegs.fpcr);
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//UNSERIALIZE_SCALAR(miscRegs.uniq);
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//UNSERIALIZE_SCALAR(miscRegs.lock_flag);
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//UNSERIALIZE_SCALAR(miscRegs.lock_addr);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(nnpc);
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#if FULL_SYSTEM
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UNSERIALIZE_ARRAY(palregs, NumIntRegs);
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UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
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UNSERIALIZE_SCALAR(intrflag);
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UNSERIALIZE_SCALAR(pal_shadow);
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#endif
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}
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#if FULL_SYSTEM
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void
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PTE::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(tag);
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SERIALIZE_SCALAR(ppn);
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SERIALIZE_SCALAR(xre);
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SERIALIZE_SCALAR(xwe);
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SERIALIZE_SCALAR(asn);
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SERIALIZE_SCALAR(asma);
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SERIALIZE_SCALAR(fonr);
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SERIALIZE_SCALAR(fonw);
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SERIALIZE_SCALAR(valid);
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}
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void
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PTE::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(tag);
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UNSERIALIZE_SCALAR(ppn);
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UNSERIALIZE_SCALAR(xre);
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UNSERIALIZE_SCALAR(xwe);
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UNSERIALIZE_SCALAR(asn);
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UNSERIALIZE_SCALAR(asma);
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UNSERIALIZE_SCALAR(fonr);
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UNSERIALIZE_SCALAR(fonw);
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UNSERIALIZE_SCALAR(valid);
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}
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#endif //FULL_SYSTEM
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