169 lines
12 KiB
Plaintext
169 lines
12 KiB
Plaintext
// Copyright (c) 2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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// All rights reserved.
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//
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// Redistribution and use of this software in source and binary forms,
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// with or without modification, are permitted provided that the
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// following conditions are met:
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//
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// The software must be used only for Non-Commercial Use which means any
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// use which is NOT directed to receiving any direct monetary
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// compensation for, or commercial advantage from such use. Illustrative
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// examples of non-commercial use are academic research, personal study,
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// teaching, education and corporate research & development.
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// Illustrative examples of commercial use are distributing products for
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// commercial advantage and providing services using the software for
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// commercial advantage.
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//
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// If you wish to use this software or functionality therein that may be
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// covered by patents for commercial use, please contact:
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// Director of Intellectual Property Licensing
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// Office of Strategy and Technology
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// Hewlett-Packard Company
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// 1501 Page Mill Road
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// Palo Alto, California 94304
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//
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// Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer. Redistributions
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// in binary form must reproduce the above copyright notice, this list of
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// conditions and the following disclaimer in the documentation and/or
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// other materials provided with the distribution. Neither the name of
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// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission. No right of
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// sublicense is granted herewith. Derivatives of the software and
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// output created using the software may be prepared, but only for
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// Non-Commercial Uses. Derivatives of the software may be shared with
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// others provided: (i) the others agree to abide by the list of
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// conditions herein which includes the Non-Commercial Use restrictions;
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// and (ii) such Derivatives of the software include the above copyright
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// notice to acknowledge the contribution from this software where
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// applicable, this list of conditions and the disclaimer below.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'sw' : ('signed int', 16),
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'uw' : ('unsigned int', 16),
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'sdw' : ('signed int', 32),
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'udw' : ('unsigned int', 32),
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'sqw' : ('signed int', 64),
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'uqw' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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}};
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def operands {{
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'SrcReg1': ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1),
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'SSrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 1),
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'SrcReg2': ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2),
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'SSrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 1),
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'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3),
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'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4),
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'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5),
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'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5),
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'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6),
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'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7),
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'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8),
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'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9),
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'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10),
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'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11),
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'Rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12),
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'Rbx': ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13),
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'Rcx': ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14),
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'Rdx': ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15),
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'Rsp': ('IntReg', 'uqw', '(INTREG_RSP)', 'IsInteger', 16),
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'Rbp': ('IntReg', 'uqw', '(INTREG_RBP)', 'IsInteger', 17),
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'Rsi': ('IntReg', 'uqw', '(INTREG_RSI)', 'IsInteger', 18),
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'Rdi': ('IntReg', 'uqw', '(INTREG_RDI)', 'IsInteger', 19),
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'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
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'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
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'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
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'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
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'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
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'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
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'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
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# This holds the condition code portion of the flag register. The
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# nccFlagBits version holds the rest.
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'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
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# These register should needs to be more protected so that later
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# instructions don't map their indexes with an old value.
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'nccFlagBits': ('ControlReg', 'uqw', 'MISCREG_RFLAGS', None, 61),
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'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 62),
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# The segment base as used by memory instructions.
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'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
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# Operands to get and set registers indexed by the operands of the
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# original instruction.
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'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100),
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'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101),
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'DebugDest': ('ControlReg', 'uqw', 'MISCREG_DR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102),
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'DebugSrc1': ('ControlReg', 'uqw', 'MISCREG_DR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 103),
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'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 104),
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'SegBaseSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 105),
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'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 106),
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'SegLimitSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 107),
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'SegSelDest': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 108),
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'SegSelSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 109),
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'SegAttrDest': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 110),
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'SegAttrSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 111),
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# Operands to access specific control registers directly.
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'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 200),
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'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 201),
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'DR7Op': ('ControlReg', 'uqw', 'MISCREG_DR7', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 202),
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'LDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSL_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 203),
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'LDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSL_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 204),
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'LDTRSel': ('ControlReg', 'uqw', 'MISCREG_TSL', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
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'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
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'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
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'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
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'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
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'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
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'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 211),
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'TscOp': ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 212),
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'M5Reg': ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None, None), 213),
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'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
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}};
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