a2d246b6b8
This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared".
1084 lines
34 KiB
C++
1084 lines
34 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#ifndef __CPU_INORDER_DYN_INST_HH__
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#define __CPU_INORDER_DYN_INST_HH__
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#include <bitset>
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#include <list>
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#include <string>
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#include "arch/isa_traits.hh"
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#include "arch/mt.hh"
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#include "arch/types.hh"
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#include "arch/utility.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/inorder/inorder_trace.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/resource.hh"
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#include "cpu/inorder/resource_sked.hh"
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#include "cpu/inorder/thread_state.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/op_class.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "debug/InOrderDynInst.hh"
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#include "mem/packet.hh"
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#include "sim/system.hh"
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#if THE_ISA == ALPHA_ISA
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#include "arch/alpha/ev5.hh"
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#endif
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/**
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* @file
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* Defines a dynamic instruction context for a inorder CPU model.
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*/
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// Forward declaration.
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class ResourceRequest;
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class Packet;
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class InOrderDynInst : public ExecContext, public RefCounted
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{
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public:
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// Binary machine instruction type.
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typedef TheISA::MachInst MachInst;
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// Extended machine instruction type
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typedef TheISA::ExtMachInst ExtMachInst;
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// Logical register index type.
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typedef TheISA::RegIndex RegIndex;
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// Integer register type.
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typedef TheISA::IntReg IntReg;
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// Floating point register type.
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typedef TheISA::FloatReg FloatReg;
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// Floating point register type.
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typedef TheISA::FloatRegBits FloatRegBits;
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// Condition code register type.
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typedef TheISA::CCReg CCReg;
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// Floating point register type.
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typedef TheISA::MiscReg MiscReg;
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typedef short int PhysRegIndex;
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/** The refcounted DynInst pointer to be used. In most cases this is
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* what should be used, and not DynInst*.
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*/
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typedef RefCountingPtr<InOrderDynInst> DynInstPtr;
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// The list of instructions iterator type.
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typedef std::list<DynInstPtr>::iterator ListIt;
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enum {
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MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
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MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
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};
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public:
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/** BaseDynInst constructor given a binary instruction.
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* @param seq_num The sequence number of the instruction.
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* @param cpu Pointer to the instruction's CPU.
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* NOTE: Must set Binary Instrution through Member Function
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*/
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InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
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InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
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/** InOrderDynInst destructor. */
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~InOrderDynInst();
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public:
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/** The sequence number of the instruction. */
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InstSeqNum seqNum;
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/** If this instruction is squashing, the number should we squash behind. */
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InstSeqNum squashSeqNum;
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enum Status {
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RegDepMapEntry, /// Instruction is entered onto the RegDepMap
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IqEntry, /// Instruction is in the IQ
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RobEntry, /// Instruction is in the ROB
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LsqEntry, /// Instruction is in the LSQ
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Completed, /// Instruction has completed
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ResultReady, /// Instruction has its result
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CanIssue, /// Instruction can issue and execute
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Issued, /// Instruction has issued
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Executed, /// Instruction has executed
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CanCommit, /// Instruction can commit
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AtCommit, /// Instruction has reached commit
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Committed, /// Instruction has committed
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Squashed, /// Instruction is squashed
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SquashedInIQ, /// Instruction is squashed in the IQ
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SquashedInLSQ, /// Instruction is squashed in the LSQ
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SquashedInROB, /// Instruction is squashed in the ROB
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RecoverInst, /// Is a recover instruction
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BlockingInst, /// Is a blocking instruction
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ThreadsyncWait, /// Is a thread synchronization instruction
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SerializeBefore, /// Needs to serialize on
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/// instructions ahead of it
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SerializeAfter, /// Needs to serialize instructions behind it
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SerializeHandled, /// Serialization has been handled
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RemoveList, /// Is Instruction on Remove List?
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NumStatus
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};
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/** The status of this BaseDynInst. Several bits can be set. */
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std::bitset<NumStatus> status;
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/** The thread this instruction is from. */
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short threadNumber;
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/** data address space ID, for loads & stores. */
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short asid;
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/** The virtual processor number */
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short virtProcNumber;
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/** The StaticInst used by this BaseDynInst. */
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StaticInstPtr staticInst;
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/** InstRecord that tracks this instructions. */
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Trace::InOrderTraceRecord *traceData;
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/** Pointer to the Impl's CPU object. */
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InOrderCPU *cpu;
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/** Pointer to the thread state. */
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InOrderThreadState *thread;
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/** The kind of fault this instruction has generated. */
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Fault fault;
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/** The memory request. */
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Request *req;
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/** Pointer to the data for the memory access. */
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uint8_t *memData;
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/** Data used for a store for operation. */
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uint64_t loadData;
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/** Data used for a store for operation. */
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uint64_t storeData;
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/** List of active resource requests for this instruction */
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std::list<ResourceRequest*> reqList;
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/** The effective virtual address (lds & stores only). */
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Addr effAddr;
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/** The effective physical address. */
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Addr physEffAddr;
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/** The memory request flags (from translation). */
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unsigned memReqFlags;
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/** How many source registers are ready. */
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unsigned readyRegs;
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enum ResultType {
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None,
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Integer,
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Float,
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FloatBits,
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Double
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};
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/** An instruction src/dest has to be one of these types */
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struct InstValue {
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IntReg intVal;
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union {
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FloatReg f;
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FloatRegBits i;
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} fpVal;
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InstValue()
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{
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intVal = 0;
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fpVal.i = 0;
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}
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};
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/** Result of an instruction execution */
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struct InstResult {
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ResultType type;
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InstValue res;
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Tick tick;
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InstResult()
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: type(None), tick(0)
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{ }
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};
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/** The source of the instruction; assumes for now that there's only one
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* destination register.
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*/
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InstValue instSrc[MaxInstSrcRegs];
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/** The result of the instruction; assumes for now that there's only one
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* destination register.
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*/
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InstResult instResult[MaxInstDestRegs];
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/** PC of this instruction. */
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TheISA::PCState pc;
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/** Predicted next PC. */
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TheISA::PCState predPC;
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/** Address to get/write data from/to */
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/* Fetching address when inst. starts, Data address for load/store after fetch*/
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Addr memAddr;
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/** Whether or not the source register is ready.
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* @todo: Not sure this should be here vs the derived class.
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*/
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bool _readySrcRegIdx[MaxInstSrcRegs];
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/** Flattened register index of the destination registers of this
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* instruction.
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*/
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TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
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/** Flattened register index of the source registers of this
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* instruction.
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*/
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TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
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/** Physical register index of the destination registers of this
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* instruction.
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*/
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PhysRegIndex _destRegIdx[MaxInstDestRegs];
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/** Physical register index of the source registers of this
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* instruction.
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*/
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PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
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/** Physical register index of the previous producers of the
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* architected destinations.
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*/
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PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
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int nextStage;
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private:
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/** Function to initialize variables in the constructors. */
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void initVars();
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public:
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Tick memTime;
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PacketDataPtr splitMemData;
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RequestPtr splitMemReq;
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int totalSize;
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int split2ndSize;
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Addr split2ndAddr;
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bool split2ndAccess;
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uint8_t split2ndData;
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PacketDataPtr split2ndDataPtr;
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unsigned split2ndFlags;
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bool splitInst;
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int splitFinishCnt;
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uint64_t *split2ndStoreDataPtr;
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bool splitInstSked;
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////////////////////////////////////////////////////////////
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//
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// BASE INSTRUCTION INFORMATION.
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//
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////////////////////////////////////////////////////////////
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std::string instName()
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{ return (staticInst) ? staticInst->getName() : "undecoded-inst"; }
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void setStaticInst(StaticInstPtr si);
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ExtMachInst getMachInst() { return staticInst->machInst; }
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/** Sets the StaticInst. */
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void setStaticInst(StaticInstPtr &static_inst);
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/** Sets the sequence number. */
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void setSeqNum(InstSeqNum seq_num) { seqNum = seq_num; }
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/** Sets the ASID. */
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void setASID(short addr_space_id) { asid = addr_space_id; }
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/** Reads the thread id. */
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short readTid() { return threadNumber; }
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/** Sets the thread id. */
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void setTid(ThreadID tid) { threadNumber = tid; }
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void setVpn(int id) { virtProcNumber = id; }
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int readVpn() { return virtProcNumber; }
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/** Sets the pointer to the thread state. */
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void setThreadState(InOrderThreadState *state) { thread = state; }
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/** Returns the thread context. */
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ThreadContext *tcBase() { return thread->getTC(); }
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/** Returns the fault type. */
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Fault getFault() { return fault; }
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/** Read this CPU's ID. */
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int cpuId() const;
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/** Read this context's system-wide ID **/
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int contextId() const { return thread->contextId(); }
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////////////////////////////////////////////////////////////
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//
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// INSTRUCTION TYPES - Forward checks to StaticInst object.
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//
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////////////////////////////////////////////////////////////
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bool isNop() const { return staticInst->isNop(); }
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bool isMemRef() const { return staticInst->isMemRef(); }
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bool isLoad() const { return staticInst->isLoad(); }
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bool isStore() const { return staticInst->isStore(); }
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bool isStoreConditional() const
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{ return staticInst->isStoreConditional(); }
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bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
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bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
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bool isInteger() const { return staticInst->isInteger(); }
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bool isFloating() const { return staticInst->isFloating(); }
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bool isControl() const { return staticInst->isControl(); }
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bool isCall() const { return staticInst->isCall(); }
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bool isReturn() const { return staticInst->isReturn(); }
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bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
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bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
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bool isCondCtrl() const { return staticInst->isCondCtrl(); }
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bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
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bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
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bool isThreadSync() const { return staticInst->isThreadSync(); }
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bool isSerializing() const { return staticInst->isSerializing(); }
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bool isSerializeBefore() const
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{ return staticInst->isSerializeBefore() || status[SerializeBefore]; }
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bool isSerializeAfter() const
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{ return staticInst->isSerializeAfter() || status[SerializeAfter]; }
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bool isMemBarrier() const { return staticInst->isMemBarrier(); }
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bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
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bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
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bool isQuiesce() const { return staticInst->isQuiesce(); }
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bool isIprAccess() const { return staticInst->isIprAccess(); }
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bool isUnverifiable() const { return staticInst->isUnverifiable(); }
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bool isSyscall() const
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{ return staticInst->isSyscall(); }
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bool isMicroop() const { return staticInst->isMicroop(); }
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bool isLastMicroop() const { return staticInst->isLastMicroop(); }
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/////////////////////////////////////////////
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//
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// RESOURCE SCHEDULING
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//
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/////////////////////////////////////////////
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typedef ThePipeline::RSkedPtr RSkedPtr;
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bool inFrontEnd;
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RSkedPtr frontSked;
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RSkedIt frontSked_end;
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RSkedPtr backSked;
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RSkedIt backSked_end;
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RSkedIt curSkedEntry;
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void setFrontSked(RSkedPtr front_sked)
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{
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frontSked = front_sked;
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frontSked_end.init(frontSked);
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frontSked_end = frontSked->end();
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//DPRINTF(InOrderDynInst, "Set FrontSked End to : %x \n" ,
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// frontSked_end.getIt()/*, frontSked->end()*/);
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//assert(frontSked_end == frontSked->end());
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// This initializes instruction to be able
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// to walk the resource schedule
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curSkedEntry.init(frontSked);
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curSkedEntry = frontSked->begin();
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}
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void setBackSked(RSkedPtr back_sked)
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{
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backSked = back_sked;
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backSked_end.init(backSked);
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backSked_end = backSked->end();
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}
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void setNextStage(int stage_num) { nextStage = stage_num; }
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int getNextStage() { return nextStage; }
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/** Print Resource Schedule */
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void printSked()
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{
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if (frontSked != NULL) {
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frontSked->print();
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}
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if (backSked != NULL) {
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backSked->print();
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}
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}
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/** Return Next Resource Stage To Be Used */
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int nextResStage()
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{
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assert((inFrontEnd && curSkedEntry != frontSked_end) ||
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(!inFrontEnd && curSkedEntry != backSked_end));
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return curSkedEntry->stageNum;
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}
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/** Return Next Resource To Be Used */
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int nextResource()
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{
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assert((inFrontEnd && curSkedEntry != frontSked_end) ||
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(!inFrontEnd && curSkedEntry != backSked_end));
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return curSkedEntry->resNum;
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}
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/** Finish using a schedule entry, increment to next entry */
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bool finishSkedEntry()
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{
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curSkedEntry++;
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if (inFrontEnd && curSkedEntry == frontSked_end) {
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DPRINTF(InOrderDynInst, "[sn:%i] Switching to "
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"back end schedule.\n", seqNum);
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assert(backSked != NULL);
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curSkedEntry.init(backSked);
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curSkedEntry = backSked->begin();
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inFrontEnd = false;
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} else if (!inFrontEnd && curSkedEntry == backSked_end) {
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return true;
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}
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DPRINTF(InOrderDynInst, "[sn:%i] Next Stage: %i "
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"Next Resource: %i.\n", seqNum, curSkedEntry->stageNum,
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curSkedEntry->resNum);
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return false;
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}
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/** Release a Resource Request (Currently Unused) */
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void releaseReq(ResourceRequest* req);
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////////////////////////////////////////////
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//
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// INSTRUCTION EXECUTION
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//
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////////////////////////////////////////////
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/** Returns the opclass of this instruction. */
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OpClass opClass() const { return staticInst->opClass(); }
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/** Executes the instruction.*/
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Fault execute();
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unsigned curResSlot;
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unsigned getCurResSlot() { return curResSlot; }
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void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
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/** Calls a syscall. */
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/** Calls hardware return from error interrupt. */
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Fault hwrei();
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/** Traps to handle specified fault. */
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void trap(const Fault &fault);
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bool simPalCheck(int palFunc);
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short syscallNum;
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/** Emulates a syscall. */
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void syscall(int64_t callnum);
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////////////////////////////////////////////////////////////
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//
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// PROGRAM COUNTERS - PC/NPC/NPC
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//
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////////////////////////////////////////////////////////////
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/** Read the PC of this instruction. */
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TheISA::PCState pcState() const { return pc; }
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/** Sets the PC of this instruction. */
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void pcState(const TheISA::PCState &_pc) { pc = _pc; }
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|
|
const Addr instAddr() { return pc.instAddr(); }
|
|
const Addr nextInstAddr() { return pc.nextInstAddr(); }
|
|
const MicroPC microPC() { return pc.microPC(); }
|
|
|
|
////////////////////////////////////////////////////////////
|
|
//
|
|
// BRANCH PREDICTION
|
|
//
|
|
////////////////////////////////////////////////////////////
|
|
/** Set the predicted target of this current instruction. */
|
|
void setPredTarg(const TheISA::PCState &predictedPC)
|
|
{ predPC = predictedPC; }
|
|
|
|
/** Returns the predicted target of the branch. */
|
|
TheISA::PCState readPredTarg() { return predPC; }
|
|
|
|
/** Returns the predicted PC immediately after the branch. */
|
|
Addr predInstAddr() { return predPC.instAddr(); }
|
|
|
|
/** Returns the predicted PC two instructions after the branch */
|
|
Addr predNextInstAddr() { return predPC.nextInstAddr(); }
|
|
|
|
/** Returns the predicted micro PC after the branch */
|
|
Addr readPredMicroPC() { return predPC.microPC(); }
|
|
|
|
/** Returns whether the instruction was predicted taken or not. */
|
|
bool predTaken() { return predictTaken; }
|
|
|
|
/** Returns whether the instruction mispredicted. */
|
|
bool
|
|
mispredicted()
|
|
{
|
|
TheISA::PCState nextPC = pc;
|
|
TheISA::advancePC(nextPC, staticInst);
|
|
return !(nextPC == predPC);
|
|
}
|
|
|
|
/** Returns the branch target address. */
|
|
TheISA::PCState branchTarget() const
|
|
{ return staticInst->branchTarget(pc); }
|
|
|
|
/** Checks whether or not this instruction has had its branch target
|
|
* calculated yet. For now it is not utilized and is hacked to be
|
|
* always false.
|
|
* @todo: Actually use this instruction.
|
|
*/
|
|
bool doneTargCalc() { return false; }
|
|
|
|
void setBranchPred(bool prediction) { predictTaken = prediction; }
|
|
|
|
int squashingStage;
|
|
|
|
bool predictTaken;
|
|
|
|
bool procDelaySlotOnMispred;
|
|
|
|
void setSquashInfo(unsigned stage_num);
|
|
|
|
////////////////////////////////////////////
|
|
//
|
|
// MEMORY ACCESS
|
|
//
|
|
////////////////////////////////////////////
|
|
|
|
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
|
|
|
|
Fault writeMem(uint8_t *data, unsigned size,
|
|
Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
/** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
|
|
* Access Only valid for memory operations.
|
|
*/
|
|
Fault initiateAcc();
|
|
|
|
/** Completes a memory access - Only valid for memory operations. */
|
|
Fault completeAcc(Packet *pkt);
|
|
|
|
/** Calculates Eff. Addr. part of a memory instruction. */
|
|
Fault calcEA();
|
|
|
|
/** Read Effective Address from instruction & do memory access */
|
|
Fault memAccess();
|
|
|
|
RequestPtr fetchMemReq;
|
|
RequestPtr dataMemReq;
|
|
|
|
bool memAddrReady;
|
|
|
|
bool validMemAddr()
|
|
{ return memAddrReady; }
|
|
|
|
void setMemAddr(Addr addr)
|
|
{ memAddr = addr; memAddrReady = true;}
|
|
|
|
void unsetMemAddr()
|
|
{ memAddrReady = false;}
|
|
|
|
Addr getMemAddr()
|
|
{ return memAddr; }
|
|
|
|
/** Sets the effective address. */
|
|
void setEA(Addr ea) { instEffAddr = ea; eaCalcDone = true; }
|
|
|
|
/** Returns the effective address. */
|
|
Addr getEA() const { return instEffAddr; }
|
|
|
|
/** Returns whether or not the eff. addr. calculation has been completed.*/
|
|
bool doneEACalc() { return eaCalcDone; }
|
|
|
|
/** Returns whether or not the eff. addr. source registers are ready.
|
|
* Assume that src registers 1..n-1 are the ones that the
|
|
* EA calc depends on. (i.e. src reg 0 is the source of the data to be
|
|
* stored)
|
|
*/
|
|
bool eaSrcsReady()
|
|
{
|
|
for (int i = 1; i < numSrcRegs(); ++i) {
|
|
if (!_readySrcRegIdx[i])
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
//////////////////////////////////////////////////
|
|
//
|
|
// SOURCE-DESTINATION REGISTER INDEXING
|
|
//
|
|
//////////////////////////////////////////////////
|
|
/** Returns the number of source registers. */
|
|
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
|
|
|
|
/** Returns the number of destination registers. */
|
|
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
|
|
|
|
// the following are used to track physical register usage
|
|
// for machines with separate int & FP reg files
|
|
int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
|
|
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
|
|
|
|
/** Returns the logical register index of the i'th destination register. */
|
|
RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
|
|
|
|
/** Returns the logical register index of the i'th source register. */
|
|
RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
|
|
|
|
//////////////////////////////////////////////////
|
|
//
|
|
// RENAME/PHYSICAL REGISTER FILE SUPPORT
|
|
//
|
|
//////////////////////////////////////////////////
|
|
/** Returns the physical register index of the i'th destination
|
|
* register.
|
|
*/
|
|
PhysRegIndex renamedDestRegIdx(int idx) const
|
|
{
|
|
return _destRegIdx[idx];
|
|
}
|
|
|
|
/** Returns the physical register index of the i'th source register. */
|
|
PhysRegIndex renamedSrcRegIdx(int idx) const
|
|
{
|
|
return _srcRegIdx[idx];
|
|
}
|
|
|
|
/** Flattens a source architectural register index into a logical index.
|
|
*/
|
|
void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
|
|
{
|
|
_flatSrcRegIdx[idx] = flattened_src;
|
|
}
|
|
|
|
/** Flattens a destination architectural register index into a logical
|
|
* index.
|
|
*/
|
|
void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
|
|
{
|
|
_flatDestRegIdx[idx] = flattened_dest;
|
|
}
|
|
|
|
/** Returns the flattened register index of the i'th destination
|
|
* register.
|
|
*/
|
|
TheISA::RegIndex flattenedDestRegIdx(int idx) const
|
|
{
|
|
return _flatDestRegIdx[idx];
|
|
}
|
|
|
|
/** Returns the flattened register index of the i'th source register */
|
|
TheISA::RegIndex flattenedSrcRegIdx(int idx) const
|
|
{
|
|
return _flatSrcRegIdx[idx];
|
|
}
|
|
|
|
/** Returns the physical register index of the previous physical register
|
|
* that remapped to the same logical register index.
|
|
*/
|
|
PhysRegIndex prevDestRegIdx(int idx) const
|
|
{
|
|
return _prevDestRegIdx[idx];
|
|
}
|
|
|
|
/** Returns if a source register is ready. */
|
|
bool isReadySrcRegIdx(int idx) const
|
|
{
|
|
return this->_readySrcRegIdx[idx];
|
|
}
|
|
|
|
/** Records that one of the source registers is ready. */
|
|
void markSrcRegReady()
|
|
{
|
|
if (++readyRegs == numSrcRegs()) {
|
|
status.set(CanIssue);
|
|
}
|
|
}
|
|
|
|
/** Marks a specific register as ready. */
|
|
void markSrcRegReady(RegIndex src_idx)
|
|
{
|
|
_readySrcRegIdx[src_idx] = true;
|
|
|
|
markSrcRegReady();
|
|
}
|
|
|
|
/** Renames a destination register to a physical register. Also records
|
|
* the previous physical register that the logical register mapped to.
|
|
*/
|
|
void renameDestReg(int idx,
|
|
PhysRegIndex renamed_dest,
|
|
PhysRegIndex previous_rename)
|
|
{
|
|
_destRegIdx[idx] = renamed_dest;
|
|
_prevDestRegIdx[idx] = previous_rename;
|
|
}
|
|
|
|
/** Renames a source logical register to the physical register which
|
|
* has/will produce that logical register's result.
|
|
* @todo: add in whether or not the source register is ready.
|
|
*/
|
|
void renameSrcReg(int idx, PhysRegIndex renamed_src)
|
|
{
|
|
_srcRegIdx[idx] = renamed_src;
|
|
}
|
|
|
|
|
|
PhysRegIndex readDestRegIdx(int idx)
|
|
{
|
|
return _destRegIdx[idx];
|
|
}
|
|
|
|
void setDestRegIdx(int idx, PhysRegIndex dest_idx)
|
|
{
|
|
_destRegIdx[idx] = dest_idx;
|
|
}
|
|
|
|
int getDestIdxNum(PhysRegIndex dest_idx)
|
|
{
|
|
for (int i=0; i < staticInst->numDestRegs(); i++) {
|
|
if (_flatDestRegIdx[i] == dest_idx)
|
|
return i;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
PhysRegIndex readSrcRegIdx(int idx)
|
|
{
|
|
return _srcRegIdx[idx];
|
|
}
|
|
|
|
void setSrcRegIdx(int idx, PhysRegIndex src_idx)
|
|
{
|
|
_srcRegIdx[idx] = src_idx;
|
|
}
|
|
|
|
int getSrcIdxNum(PhysRegIndex src_idx)
|
|
{
|
|
for (int i=0; i < staticInst->numSrcRegs(); i++) {
|
|
if (_srcRegIdx[i] == src_idx)
|
|
return i;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
//
|
|
// SOURCE-DESTINATION REGISTER VALUES
|
|
//
|
|
////////////////////////////////////////////////////
|
|
|
|
/** Functions that sets an integer or floating point
|
|
* source register to a value. */
|
|
void setIntSrc(int idx, uint64_t val);
|
|
void setFloatSrc(int idx, FloatReg val);
|
|
void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
|
|
|
|
TheISA::IntReg* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
|
|
uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
|
|
|
|
/** These Instructions read a integer/float/misc. source register
|
|
* value in the instruction. The instruction's execute function will
|
|
* call these and it is the interface that is used by the ISA descr.
|
|
* language (which is why the name isnt readIntSrc(...)) Note: That
|
|
* the source reg. value is set using the setSrcReg() function.
|
|
*/
|
|
IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid);
|
|
IntReg readIntRegOperand(const StaticInst *si, int idx) {
|
|
return readIntRegOperand(si, idx, 0);
|
|
}
|
|
FloatReg readFloatRegOperand(const StaticInst *si, int idx);
|
|
TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
|
|
MiscReg readMiscReg(int misc_reg);
|
|
MiscReg readMiscRegNoEffect(int misc_reg);
|
|
MiscReg readMiscRegOperand(const StaticInst *si, int idx);
|
|
MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
|
|
|
|
/** Returns the result value instruction. */
|
|
ResultType resultType(int idx)
|
|
{
|
|
return instResult[idx].type;
|
|
}
|
|
|
|
IntReg readIntResult(int idx)
|
|
{
|
|
return instResult[idx].res.intVal;
|
|
}
|
|
|
|
FloatReg readFloatResult(int idx)
|
|
{
|
|
return instResult[idx].res.fpVal.f;
|
|
}
|
|
|
|
FloatRegBits readFloatBitsResult(int idx)
|
|
{
|
|
return instResult[idx].res.fpVal.i;
|
|
}
|
|
|
|
CCReg readCCResult(int idx)
|
|
{
|
|
return instResult[idx].res.intVal;
|
|
}
|
|
|
|
Tick readResultTime(int idx) { return instResult[idx].tick; }
|
|
|
|
IntReg* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; }
|
|
|
|
/** This is the interface that an instruction will use to write
|
|
* it's destination register.
|
|
*/
|
|
void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
|
|
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
|
|
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
|
TheISA::FloatRegBits val);
|
|
void setMiscReg(int misc_reg, const MiscReg &val);
|
|
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
|
|
void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
|
|
void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
|
|
const MiscReg &val);
|
|
|
|
MiscReg readRegOtherThread(int idx, ThreadID tid);
|
|
void setRegOtherThread(int idx, MiscReg val, ThreadID tid);
|
|
|
|
/** Returns the number of consecutive store conditional failures. */
|
|
unsigned int readStCondFailures() const
|
|
{ return thread->storeCondFailures; }
|
|
|
|
/** Sets the number of consecutive store conditional failures. */
|
|
void setStCondFailures(unsigned int sc_failures)
|
|
{ thread->storeCondFailures = sc_failures; }
|
|
|
|
//////////////////////////////////////////////////////////////
|
|
//
|
|
// INSTRUCTION STATUS FLAGS (READ/SET)
|
|
//
|
|
//////////////////////////////////////////////////////////////
|
|
/** Sets this instruction as entered on the CPU Reg Dep Map */
|
|
void setRegDepEntry() { status.set(RegDepMapEntry); }
|
|
|
|
/** Unsets this instruction as entered on the CPU Reg Dep Map */
|
|
void clearRegDepEntry() { status.reset(RegDepMapEntry); }
|
|
|
|
/** Returns whether or not the entry is on the CPU Reg Dep Map */
|
|
bool isRegDepEntry() const { return status[RegDepMapEntry]; }
|
|
|
|
/** Sets this instruction as entered on the CPU Reg Dep Map */
|
|
void setRemoveList() { status.set(RemoveList); }
|
|
|
|
/** Returns whether or not the entry is on the CPU Reg Dep Map */
|
|
bool isRemoveList() const { return status[RemoveList]; }
|
|
|
|
/** Sets this instruction as completed. */
|
|
void setCompleted() { status.set(Completed); }
|
|
|
|
/** Returns whether or not this instruction is completed. */
|
|
bool isCompleted() const { return status[Completed]; }
|
|
|
|
/** Marks the result as ready. */
|
|
void setResultReady() { status.set(ResultReady); }
|
|
|
|
/** Returns whether or not the result is ready. */
|
|
bool isResultReady() const { return status[ResultReady]; }
|
|
|
|
/** Sets this instruction as ready to issue. */
|
|
void setCanIssue() { status.set(CanIssue); }
|
|
|
|
/** Returns whether or not this instruction is ready to issue. */
|
|
bool readyToIssue() const { return status[CanIssue]; }
|
|
|
|
/** Sets this instruction as issued from the IQ. */
|
|
void setIssued() { status.set(Issued); }
|
|
|
|
/** Returns whether or not this instruction has issued. */
|
|
bool isIssued() const { return status[Issued]; }
|
|
|
|
/** Sets this instruction as executed. */
|
|
void setExecuted() { status.set(Executed); }
|
|
|
|
/** Returns whether or not this instruction has executed. */
|
|
bool isExecuted() const { return status[Executed]; }
|
|
|
|
/** Sets this instruction as ready to commit. */
|
|
void setCanCommit() { status.set(CanCommit); }
|
|
|
|
/** Clears this instruction as being ready to commit. */
|
|
void clearCanCommit() { status.reset(CanCommit); }
|
|
|
|
/** Returns whether or not this instruction is ready to commit. */
|
|
bool readyToCommit() const { return status[CanCommit]; }
|
|
|
|
void setAtCommit() { status.set(AtCommit); }
|
|
|
|
bool isAtCommit() { return status[AtCommit]; }
|
|
|
|
/** Sets this instruction as committed. */
|
|
void setCommitted() { status.set(Committed); }
|
|
|
|
/** Returns whether or not this instruction is committed. */
|
|
bool isCommitted() const { return status[Committed]; }
|
|
|
|
/** Sets this instruction as squashed. */
|
|
void setSquashed() { status.set(Squashed); }
|
|
|
|
/** Returns whether or not this instruction is squashed. */
|
|
bool isSquashed() const { return status[Squashed]; }
|
|
|
|
/** Temporarily sets this instruction as a serialize before instruction. */
|
|
void setSerializeBefore() { status.set(SerializeBefore); }
|
|
|
|
/** Clears the serializeBefore part of this instruction. */
|
|
void clearSerializeBefore() { status.reset(SerializeBefore); }
|
|
|
|
/** Checks if this serializeBefore is only temporarily set. */
|
|
bool isTempSerializeBefore() { return status[SerializeBefore]; }
|
|
|
|
/** Temporarily sets this instruction as a serialize after instruction. */
|
|
void setSerializeAfter() { status.set(SerializeAfter); }
|
|
|
|
/** Clears the serializeAfter part of this instruction.*/
|
|
void clearSerializeAfter() { status.reset(SerializeAfter); }
|
|
|
|
/** Checks if this serializeAfter is only temporarily set. */
|
|
bool isTempSerializeAfter() { return status[SerializeAfter]; }
|
|
|
|
/** Sets the serialization part of this instruction as handled. */
|
|
void setSerializeHandled() { status.set(SerializeHandled); }
|
|
|
|
/** Checks if the serialization part of this instruction has been
|
|
* handled. This does not apply to the temporary serializing
|
|
* state; it only applies to this instruction's own permanent
|
|
* serializing state.
|
|
*/
|
|
bool isSerializeHandled() { return status[SerializeHandled]; }
|
|
|
|
private:
|
|
/** Instruction effective address.
|
|
* @todo: Consider if this is necessary or not.
|
|
*/
|
|
Addr instEffAddr;
|
|
|
|
/** Whether or not the effective address calculation is completed.
|
|
* @todo: Consider if this is necessary or not.
|
|
*/
|
|
bool eaCalcDone;
|
|
|
|
public:
|
|
/** Load queue index. */
|
|
int16_t lqIdx;
|
|
|
|
/** Store queue index. */
|
|
int16_t sqIdx;
|
|
|
|
/** Iterator pointing to this BaseDynInst in the list of all insts. */
|
|
ListIt instListIt;
|
|
|
|
bool onInstList;
|
|
|
|
/** Returns iterator to this instruction in the list of all insts. */
|
|
ListIt getInstListIt() { return instListIt; }
|
|
|
|
/** Sets iterator for this instruction in the list of all insts. */
|
|
void setInstListIt(ListIt _instListIt) { onInstList = true; instListIt = _instListIt; }
|
|
|
|
/** Count of total number of dynamic instructions. */
|
|
static int instcount;
|
|
|
|
void resetInstCount();
|
|
|
|
/** Dumps out contents of this BaseDynInst. */
|
|
void dump();
|
|
|
|
/** Dumps out contents of this BaseDynInst into given string. */
|
|
void dump(std::string &outstring);
|
|
|
|
//inline int curCount() { return curCount(); }
|
|
|
|
|
|
CCReg readCCRegOperand(const StaticInst *si, int idx) {
|
|
panic("readCCRegOperand unimplemented");
|
|
}
|
|
|
|
void setCCRegOperand(const StaticInst *si, int idx, CCReg val) {
|
|
panic("setCCRegOperand unimplemented");
|
|
}
|
|
|
|
void setPredicate(bool val) {
|
|
panic("setPredicate unimplemented");
|
|
}
|
|
|
|
bool readPredicate() {
|
|
panic("readPredicate unimplemented");
|
|
}
|
|
|
|
void demapPage(Addr vaddr, uint64_t asn) {
|
|
panic("demapPage unimplemented");
|
|
}
|
|
};
|
|
|
|
|
|
#endif // __CPU_BASE_DYN_INST_HH__
|