a2d246b6b8
This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared".
583 lines
19 KiB
Plaintext
583 lines
19 KiB
Plaintext
// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Ali Saidi
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// Gabe Black
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// Steve Reinhardt
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////////////////////////////////////////////////////////////////////
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//
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// Base class for sparc instructions, and some support functions
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//
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output header {{
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union CondCodes
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{
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struct
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{
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uint8_t c:1;
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uint8_t v:1;
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uint8_t z:1;
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uint8_t n:1;
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};
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uint32_t bits;
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};
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enum CondTest
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{
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Always=0x8,
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Never=0x0,
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NotEqual=0x9,
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Equal=0x1,
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Greater=0xA,
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LessOrEqual=0x2,
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GreaterOrEqual=0xB,
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Less=0x3,
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GreaterUnsigned=0xC,
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LessOrEqualUnsigned=0x4,
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CarryClear=0xD,
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CarrySet=0x5,
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Positive=0xE,
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Negative=0x6,
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OverflowClear=0xF,
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OverflowSet=0x7
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};
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enum FpCondTest
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{
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FAlways=0x8,
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FNever=0x0,
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FUnordered=0x7,
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FGreater=0x6,
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FUnorderedOrGreater=0x5,
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FLess=0x4,
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FUnorderedOrLess=0x3,
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FLessOrGreater=0x2,
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FNotEqual=0x1,
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FEqual=0x9,
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FUnorderedOrEqual=0xA,
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FGreaterOrEqual=0xB,
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FUnorderedOrGreaterOrEqual=0xC,
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FLessOrEqual=0xD,
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FUnorderedOrLessOrEqual=0xE,
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FOrdered=0xF
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};
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extern const char *CondTestAbbrev[];
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/**
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* Base class for all SPARC static instructions.
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*/
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class SparcStaticInst : public StaticInst
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{
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protected:
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// Constructor.
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SparcStaticInst(const char *mnem,
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ExtMachInst _machInst, OpClass __opClass)
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: StaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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void printReg(std::ostream &os, int reg) const;
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void printSrcReg(std::ostream &os, int reg) const;
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void printDestReg(std::ostream &os, int reg) const;
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void printRegArray(std::ostream &os,
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const RegIndex indexArray[], int num) const;
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void advancePC(SparcISA::PCState &pcState) const;
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};
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bool passesFpCondition(uint32_t fcc, uint32_t condition);
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bool passesCondition(uint32_t codes, uint32_t condition);
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inline int64_t
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sign_ext(uint64_t data, int origWidth)
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{
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int shiftAmount = 64 - origWidth;
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return (((int64_t)data) << shiftAmount) >> shiftAmount;
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}
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}};
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output decoder {{
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const char *CondTestAbbrev[] =
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{
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"nev", // Never
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"e", // Equal
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"le", // Less or Equal
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"l", // Less
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"leu", // Less or Equal Unsigned
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"c", // Carry set
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"n", // Negative
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"o", // Overflow set
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"a", // Always
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"ne", // Not Equal
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"g", // Greater
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"ge", // Greater or Equal
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"gu", // Greater Unsigned
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"cc", // Carry clear
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"p", // Positive
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"oc" // Overflow Clear
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};
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}};
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def template ROrImmDecode {{
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{
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return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
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: (SparcStaticInst *)(new %(class_name)s(machInst)));
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}
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}};
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output header {{
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union DoubleSingle
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{
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double d;
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uint64_t ui;
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uint32_t s[2];
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DoubleSingle(double _d) : d(_d)
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{}
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DoubleSingle(uint64_t _ui) : ui(_ui)
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{}
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DoubleSingle(uint32_t _s0, uint32_t _s1)
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{
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s[0] = _s0;
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s[1] = _s1;
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}
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};
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}};
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let {{
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def filterDoubles(code):
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assignRE = re.compile(r'\s*=(?!=)', re.MULTILINE)
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for opName in ("Frd", "Frs1", "Frs2", "Frd_N"):
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next_pos = 0
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operandsREString = (r'''
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(?<!\w) # neg. lookbehind assertion: prevent partial matches
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((%s)(?:_([^\W_]+))?) # match: operand with optional '.' then suffix
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(?!\w) # neg. lookahead assertion: prevent partial matches
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''' % opName)
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operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
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is_src = False
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is_dest = False
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extension = None
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foundOne = False
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while 1:
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match = operandsRE.search(code, next_pos)
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if not match:
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break
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foundOne = True
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op = match.groups()
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(op_full, op_base, op_ext) = op
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is_dest_local = (assignRE.match(code, match.end()) != None)
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is_dest = is_dest or is_dest_local
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is_src = is_src or not is_dest_local
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if extension and extension != op_ext:
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raise Exception, "Inconsistent extensions in double filter."
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extension = op_ext
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next_pos = match.end()
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if foundOne:
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# Get rid of any unwanted extension
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code = operandsRE.sub(op_base, code)
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is_int = False
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member = "d"
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if extension in ("sb", "ub", "shw", "uhw", "sw", "uw", "sdw", "udw"):
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is_int = True
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member = "ui"
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if is_src:
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code = ("%s = DoubleSingle(%s_high, %s_low).%s;" % \
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(opName, opName, opName, member)) + code
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if is_dest:
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code += '''
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%s_low = DoubleSingle(%s).s[1];
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%s_high = DoubleSingle(%s).s[0];''' % \
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(opName, opName, opName, opName)
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if is_int:
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code = ("uint64_t %s;" % opName) + code
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else:
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code = ("double %s;" % opName) + code
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return code
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}};
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let {{
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def splitOutImm(code):
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matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>_[^\W_]+)?')
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rOrImmMatch = matcher.search(code)
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if (rOrImmMatch == None):
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return (False, code, '', '', '')
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rString = rOrImmMatch.group("rNum")
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if (rOrImmMatch.group("typeQual") != None):
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rString += rOrImmMatch.group("typeQual")
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iString = rOrImmMatch.group("iNum")
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orig_code = code
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code = matcher.sub('Rs' + rString, orig_code)
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imm_code = matcher.sub('imm', orig_code)
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return (True, code, imm_code, rString, iString)
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}};
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output decoder {{
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inline void printMnemonic(std::ostream &os, const char * mnemonic)
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{
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ccprintf(os, "\t%s ", mnemonic);
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}
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void SparcStaticInst::printRegArray(std::ostream &os,
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const RegIndex indexArray[], int num) const
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{
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if (num <= 0)
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return;
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printReg(os, indexArray[0]);
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for (int x = 1; x < num; x++) {
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os << ", ";
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printReg(os, indexArray[x]);
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}
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}
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void
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SparcStaticInst::advancePC(SparcISA::PCState &pcState) const
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{
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pcState.advance();
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}
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void
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SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
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{
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if (_numSrcRegs > reg)
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printReg(os, _srcRegIdx[reg]);
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}
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void
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SparcStaticInst::printDestReg(std::ostream &os, int reg) const
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{
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if (_numDestRegs > reg)
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printReg(os, _destRegIdx[reg]);
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}
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void
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SparcStaticInst::printReg(std::ostream &os, int reg) const
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{
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const int MaxGlobal = 8;
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const int MaxOutput = 16;
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const int MaxLocal = 24;
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const int MaxInput = 32;
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const int MaxMicroReg = 40;
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if (reg < FP_Reg_Base) {
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// If we used a register from the next or previous window,
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// take out the offset.
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while (reg >= MaxMicroReg)
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reg -= MaxMicroReg;
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if (reg == FramePointerReg)
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ccprintf(os, "%%fp");
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else if (reg == StackPointerReg)
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ccprintf(os, "%%sp");
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else if (reg < MaxGlobal)
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ccprintf(os, "%%g%d", reg);
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else if (reg < MaxOutput)
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ccprintf(os, "%%o%d", reg - MaxGlobal);
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else if (reg < MaxLocal)
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ccprintf(os, "%%l%d", reg - MaxOutput);
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else if (reg < MaxInput)
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ccprintf(os, "%%i%d", reg - MaxLocal);
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else if (reg < MaxMicroReg)
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ccprintf(os, "%%u%d", reg - MaxInput);
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// The fake int regs that are really control regs
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else {
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switch (reg - MaxMicroReg) {
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case 1:
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ccprintf(os, "%%y");
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break;
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case 2:
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ccprintf(os, "%%ccr");
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break;
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case 3:
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ccprintf(os, "%%cansave");
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break;
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case 4:
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ccprintf(os, "%%canrestore");
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break;
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case 5:
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ccprintf(os, "%%cleanwin");
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break;
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case 6:
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ccprintf(os, "%%otherwin");
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break;
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case 7:
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ccprintf(os, "%%wstate");
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break;
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}
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}
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} else if (reg < Misc_Reg_Base) {
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ccprintf(os, "%%f%d", reg - FP_Reg_Base);
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} else {
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switch (reg - Misc_Reg_Base) {
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case MISCREG_ASI:
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ccprintf(os, "%%asi");
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break;
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case MISCREG_FPRS:
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ccprintf(os, "%%fprs");
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break;
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case MISCREG_PCR:
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ccprintf(os, "%%pcr");
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break;
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case MISCREG_PIC:
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ccprintf(os, "%%pic");
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break;
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case MISCREG_GSR:
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ccprintf(os, "%%gsr");
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break;
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case MISCREG_SOFTINT:
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ccprintf(os, "%%softint");
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break;
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case MISCREG_SOFTINT_SET:
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ccprintf(os, "%%softint_set");
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break;
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case MISCREG_SOFTINT_CLR:
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ccprintf(os, "%%softint_clr");
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break;
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case MISCREG_TICK_CMPR:
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ccprintf(os, "%%tick_cmpr");
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break;
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case MISCREG_STICK:
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ccprintf(os, "%%stick");
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break;
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case MISCREG_STICK_CMPR:
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ccprintf(os, "%%stick_cmpr");
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break;
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case MISCREG_TPC:
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ccprintf(os, "%%tpc");
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break;
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case MISCREG_TNPC:
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ccprintf(os, "%%tnpc");
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break;
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case MISCREG_TSTATE:
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ccprintf(os, "%%tstate");
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break;
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case MISCREG_TT:
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ccprintf(os, "%%tt");
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break;
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case MISCREG_TICK:
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ccprintf(os, "%%tick");
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break;
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case MISCREG_TBA:
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ccprintf(os, "%%tba");
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break;
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case MISCREG_PSTATE:
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ccprintf(os, "%%pstate");
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break;
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case MISCREG_TL:
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ccprintf(os, "%%tl");
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break;
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case MISCREG_PIL:
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ccprintf(os, "%%pil");
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break;
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case MISCREG_CWP:
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ccprintf(os, "%%cwp");
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break;
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case MISCREG_GL:
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ccprintf(os, "%%gl");
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break;
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case MISCREG_HPSTATE:
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ccprintf(os, "%%hpstate");
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break;
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case MISCREG_HTSTATE:
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ccprintf(os, "%%htstate");
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break;
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case MISCREG_HINTP:
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ccprintf(os, "%%hintp");
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break;
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case MISCREG_HTBA:
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ccprintf(os, "%%htba");
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break;
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case MISCREG_HSTICK_CMPR:
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ccprintf(os, "%%hstick_cmpr");
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break;
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case MISCREG_HVER:
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ccprintf(os, "%%hver");
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break;
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case MISCREG_STRAND_STS_REG:
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ccprintf(os, "%%strand_sts_reg");
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break;
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case MISCREG_FSR:
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ccprintf(os, "%%fsr");
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break;
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default:
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ccprintf(os, "%%ctrl%d", reg - Misc_Reg_Base);
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}
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}
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}
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std::string
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SparcStaticInst::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, mnemonic);
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// just print the first two source regs... if there's
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// a third one, it's a read-modify-write dest (Rc),
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// e.g. for CMOVxx
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if (_numSrcRegs > 0)
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printReg(ss, _srcRegIdx[0]);
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if (_numSrcRegs > 1) {
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ss << ",";
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printReg(ss, _srcRegIdx[1]);
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}
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// just print the first dest... if there's a second one,
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// it's generally implicit
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if (_numDestRegs > 0) {
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if (_numSrcRegs > 0)
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ss << ",";
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printReg(ss, _destRegIdx[0]);
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}
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return ss.str();
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}
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bool
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passesFpCondition(uint32_t fcc, uint32_t condition)
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{
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bool u = (fcc == 3);
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bool g = (fcc == 2);
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bool l = (fcc == 1);
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bool e = (fcc == 0);
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switch (condition) {
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case FAlways:
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return 1;
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case FNever:
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return 0;
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case FUnordered:
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return u;
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case FGreater:
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return g;
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case FUnorderedOrGreater:
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return u || g;
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case FLess:
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return l;
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case FUnorderedOrLess:
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return u || l;
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case FLessOrGreater:
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return l || g;
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case FNotEqual:
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return l || g || u;
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case FEqual:
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return e;
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case FUnorderedOrEqual:
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return u || e;
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case FGreaterOrEqual:
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return g || e;
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case FUnorderedOrGreaterOrEqual:
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return u || g || e;
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case FLessOrEqual:
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return l || e;
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case FUnorderedOrLessOrEqual:
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return u || l || e;
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case FOrdered:
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return e || l || g;
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}
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panic("Tried testing condition nonexistant "
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"condition code %d", condition);
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}
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|
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bool
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passesCondition(uint32_t codes, uint32_t condition)
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{
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CondCodes condCodes;
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condCodes.bits = 0;
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condCodes.c = codes & 0x1 ? 1 : 0;
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condCodes.v = codes & 0x2 ? 1 : 0;
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condCodes.z = codes & 0x4 ? 1 : 0;
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condCodes.n = codes & 0x8 ? 1 : 0;
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switch (condition) {
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case Always:
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return true;
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case Never:
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return false;
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case NotEqual:
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return !condCodes.z;
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case Equal:
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return condCodes.z;
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case Greater:
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return !(condCodes.z | (condCodes.n ^ condCodes.v));
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case LessOrEqual:
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return condCodes.z | (condCodes.n ^ condCodes.v);
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case GreaterOrEqual:
|
|
return !(condCodes.n ^ condCodes.v);
|
|
case Less:
|
|
return (condCodes.n ^ condCodes.v);
|
|
case GreaterUnsigned:
|
|
return !(condCodes.c | condCodes.z);
|
|
case LessOrEqualUnsigned:
|
|
return (condCodes.c | condCodes.z);
|
|
case CarryClear:
|
|
return !condCodes.c;
|
|
case CarrySet:
|
|
return condCodes.c;
|
|
case Positive:
|
|
return !condCodes.n;
|
|
case Negative:
|
|
return condCodes.n;
|
|
case OverflowClear:
|
|
return !condCodes.v;
|
|
case OverflowSet:
|
|
return condCodes.v;
|
|
}
|
|
panic("Tried testing condition nonexistant "
|
|
"condition code %d", condition);
|
|
}
|
|
}};
|
|
|
|
output exec {{
|
|
/// Check "FP enabled" machine status bit. Called when executing any FP
|
|
/// instruction.
|
|
/// @retval Full-system mode: NoFault if FP is enabled, FpDisabled
|
|
/// if not. Non-full-system mode: always returns NoFault.
|
|
static inline Fault
|
|
checkFpEnableFault(CPU_EXEC_CONTEXT *xc)
|
|
{
|
|
if (FullSystem) {
|
|
PSTATE pstate = xc->readMiscReg(MISCREG_PSTATE);
|
|
if (pstate.pef && xc->readMiscReg(MISCREG_FPRS) & 0x4) {
|
|
return NoFault;
|
|
} else {
|
|
return std::make_shared<FpDisabled>();
|
|
}
|
|
} else {
|
|
return NoFault;
|
|
}
|
|
}
|
|
}};
|
|
|
|
|