a2d246b6b8
This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared".
382 lines
12 KiB
C++
382 lines
12 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2007 MIPS Technologies, Inc.
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Korey Sewell
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////////////////////////////////////////////////////////////////////
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//
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// Integer operate instructions
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//
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output header {{
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#include <iostream>
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using namespace std;
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/**
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* Base class for integer operations.
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*/
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class IntOp : public MipsStaticInst
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{
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protected:
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/// Constructor
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IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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MipsStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class HiLoOp: public IntOp
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{
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protected:
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/// Constructor
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HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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IntOp(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class HiLoRsSelOp: public HiLoOp
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{
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protected:
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/// Constructor
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HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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HiLoOp(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class HiLoRdSelOp: public HiLoOp
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{
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protected:
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/// Constructor
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HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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HiLoOp(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class HiLoRdSelValOp: public HiLoOp
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{
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protected:
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/// Constructor
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HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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HiLoOp(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class IntImmOp : public MipsStaticInst
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{
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protected:
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int16_t imm;
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int32_t sextImm;
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uint32_t zextImm;
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/// Constructor
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IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
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sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
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{
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//If Bit 15 is 1 then Sign Extend
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int32_t temp = sextImm & 0x00008000;
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if (temp > 0 && strcmp(mnemonic,"lui") != 0) {
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sextImm |= 0xFFFF0000;
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}
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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// HiLo instruction class execute method template.
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def template HiLoExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// HiLoRsSel instruction class execute method template.
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def template HiLoRsSelExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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if( ACSRC > 0 && !isDspEnabled(xc) )
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{
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fault = std::make_shared<DspStateDisabledFault>();
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}
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else
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{
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%(op_rd)s;
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%(code)s;
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// HiLoRdSel instruction class execute method template.
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def template HiLoRdSelExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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if( ACDST > 0 && !isDspEnabled(xc) )
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{
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fault = std::make_shared<DspStateDisabledFault>();
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}
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else
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{
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%(op_rd)s;
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%(code)s;
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}
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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//Outputs to decoder.cc
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output decoder {{
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std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// just print the first dest... if there's a second one,
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// it's generally implicit
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if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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ss << ", ";
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}
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// just print the first two source regs... if there's
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// a third one, it's a read-modify-write dest (Rc),
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// e.g. for CMOVxx
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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}
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if (_numSrcRegs > 1) {
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ss << ", ";
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printReg(ss, _srcRegIdx[1]);
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}
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return ss.str();
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}
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std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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//Destination Registers are implicit for HI/LO ops
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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}
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if (_numSrcRegs > 1) {
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ss << ", ";
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printReg(ss, _srcRegIdx[1]);
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}
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return ss.str();
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}
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std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
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printReg(ss, _destRegIdx[0]);
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} else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
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printReg(ss, _srcRegIdx[0]);
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}
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return ss.str();
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}
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std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
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printReg(ss, _destRegIdx[0]);
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} else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
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printReg(ss, _srcRegIdx[0]);
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}
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return ss.str();
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}
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std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
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printReg(ss, _destRegIdx[0]);
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} else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
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printReg(ss, _srcRegIdx[0]);
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}
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return ss.str();
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}
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std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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}
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ss << ", ";
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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ss << ", ";
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}
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if(strcmp(mnemonic,"lui") == 0)
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ccprintf(ss, "0x%x ", sextImm);
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else
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ss << (int) sextImm;
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return ss.str();
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}
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}};
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def format IntOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'IntOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = RegNopCheckDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format IntImmOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = ImmNopCheckDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format HiLoRsSelOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = HiLoRsSelExecute.subst(iop)
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}};
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def format HiLoRdSelOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = HiLoRdSelExecute.subst(iop)
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}};
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def format HiLoRdSelValOp(code, *opt_flags) {{
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if '_sd' in code:
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code = 'int64_t ' + code
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elif '_ud' in code:
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code = 'uint64_t ' + code
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code += 'HI_RD_SEL = val<63:32>;\n'
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code += 'LO_RD_SEL = val<31:0>;\n'
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iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = HiLoRdSelExecute.subst(iop)
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}};
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def format HiLoOp(code, *opt_flags) {{
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iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = HiLoExecute.subst(iop)
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}};
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