e5b7b6780f
This patch fixes the order that packets gets pushed into the output fifo of etherswitch. If two packets arrive at the same tick to the etherswitch, we sort and push them based on their source port id. In dist-gem5 simulations, if there is no ordering inforced while two packets arrive at the same tick, it can lead to non-deterministic simulations Committed by Jason Lowe-Power <power.jg@gmail.com> |
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arm-ccregs.py | ||
arm-contextidr-el2.py | ||
arm-gem5-gic-ext.py | ||
arm-hdlcd-upgrade.py | ||
arm-miscreg-teehbr.py | ||
armv8.py | ||
cpu-pid.py | ||
dvfs-perflevel.py | ||
etherswitch.py | ||
ide-dma-abort.py | ||
isa-is-simobject.py | ||
memory-per-range.py | ||
multiple-event-queues.py | ||
process-fdmap-rename.py | ||
remove-arm-cpsr-mode-miscreg.py | ||
ruby-block-size-bytes.py | ||
smt-interrupts.py | ||
x86-add-tlb.py |