628 lines
72 KiB
Text
628 lines
72 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000100 # Number of seconds simulated
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sim_ticks 100232 # Number of ticks simulated
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final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000 # Frequency of simulated ticks
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host_inst_rate 93908 # Simulator instruction rate (inst/s)
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host_op_rate 93894 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1668107 # Simulator tick rate (ticks/s)
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host_mem_usage 455812 # Number of bytes of host memory used
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host_seconds 0.06 # Real time elapsed on the host
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sim_insts 5641 # Number of instructions simulated
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sim_ops 5641 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1 # Clock period in ticks
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system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
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system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory
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system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory
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system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory
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system.mem_ctrls.bytes_written::total 93952 # Number of bytes written to this memory
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system.mem_ctrls.num_reads::ruby.dir_cntrl0 1472 # Number of read requests responded to by this memory
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system.mem_ctrls.num_reads::total 1472 # Number of read requests responded to by this memory
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system.mem_ctrls.num_writes::ruby.dir_cntrl0 1468 # Number of write requests responded to by this memory
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system.mem_ctrls.num_writes::total 1468 # Number of write requests responded to by this memory
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system.mem_ctrls.bw_read::ruby.dir_cntrl0 939899433 # Total read bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_read::total 939899433 # Total read bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_write::ruby.dir_cntrl0 937345359 # Write bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_write::total 937345359 # Write bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_total::ruby.dir_cntrl0 1877244792 # Total bandwidth to/from this memory (bytes/s)
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system.mem_ctrls.bw_total::total 1877244792 # Total bandwidth to/from this memory (bytes/s)
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system.mem_ctrls.readReqs 1472 # Number of read requests accepted
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system.mem_ctrls.writeReqs 1468 # Number of write requests accepted
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system.mem_ctrls.readBursts 1472 # Number of DRAM read bursts, including those serviced by the write queue
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system.mem_ctrls.writeBursts 1468 # Number of DRAM write bursts, including those merged in the write queue
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system.mem_ctrls.bytesReadDRAM 58752 # Total number of bytes read from DRAM
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system.mem_ctrls.bytesReadWrQ 35456 # Total number of bytes read from write queue
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system.mem_ctrls.bytesWritten 60352 # Total number of bytes written to DRAM
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system.mem_ctrls.bytesReadSys 94208 # Total read bytes from the system interface side
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system.mem_ctrls.bytesWrittenSys 93952 # Total written bytes from the system interface side
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system.mem_ctrls.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue
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system.mem_ctrls.mergedWrBursts 502 # Number of DRAM write bursts merged with an existing one
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system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::7 81 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::9 245 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::10 98 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::11 45 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::12 114 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::14 154 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::15 14 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::0 34 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::7 74 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::9 247 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::10 100 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::11 46 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::13 49 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::14 178 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts
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system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
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system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
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system.mem_ctrls.totGap 100183 # Total gap between requests
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system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::6 1472 # Read request sizes (log2)
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system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::6 1468 # Write request sizes (log2)
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system.mem_ctrls.rdQLenPdf::0 918 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::20 67 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::21 61 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::22 59 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::25 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::26 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::27 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::28 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::29 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::30 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::31 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::32 58 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.mem_ctrls.bytesPerActivate::samples 336 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::mean 348.571429 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::gmean 224.382213 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::stdev 328.447975 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::0-127 77 22.92% 22.92% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::128-255 103 30.65% 53.57% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::256-383 48 14.29% 67.86% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::384-511 26 7.74% 75.60% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::512-639 11 3.27% 78.87% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::640-767 8 2.38% 81.25% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::768-895 13 3.87% 85.12% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::896-1023 7 2.08% 87.20% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::1024-1151 43 12.80% 100.00% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::total 336 # Bytes accessed per row activation
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system.mem_ctrls.rdPerTurnAround::samples 58 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::mean 15.706897 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::gmean 15.549891 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::stdev 2.720995 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::12-13 5 8.62% 8.62% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::14-15 26 44.83% 53.45% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::16-17 25 43.10% 96.55% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::18-19 1 1.72% 98.28% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::34-35 1 1.72% 100.00% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::total 58 # Reads before turning the bus around for writes
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system.mem_ctrls.wrPerTurnAround::samples 58 # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::mean 16.258621 # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::gmean 16.240724 # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::stdev 0.806995 # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::16 52 89.66% 89.66% # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::18 4 6.90% 96.55% # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::19 1 1.72% 98.28% # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::20 1 1.72% 100.00% # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::total 58 # Writes before turning the bus around for reads
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system.mem_ctrls.totQLat 12638 # Total ticks spent queuing
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system.mem_ctrls.totMemAccLat 30080 # Total ticks spent from burst creation until serviced by the DRAM
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system.mem_ctrls.totBusLat 4590 # Total ticks spent in databus transfers
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system.mem_ctrls.avgQLat 13.77 # Average queueing delay per DRAM burst
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system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
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system.mem_ctrls.avgMemAccLat 32.77 # Average memory access latency per DRAM burst
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system.mem_ctrls.avgRdBW 586.16 # Average DRAM read bandwidth in MiByte/s
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system.mem_ctrls.avgWrBW 602.12 # Average achieved write bandwidth in MiByte/s
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system.mem_ctrls.avgRdBWSys 939.90 # Average system read bandwidth in MiByte/s
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system.mem_ctrls.avgWrBWSys 937.35 # Average system write bandwidth in MiByte/s
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system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.mem_ctrls.busUtil 9.28 # Data bus utilization in percentage
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system.mem_ctrls.busUtilRead 4.58 # Data bus utilization in percentage for reads
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system.mem_ctrls.busUtilWrite 4.70 # Data bus utilization in percentage for writes
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system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.mem_ctrls.avgWrQLen 25.54 # Average write queue length when enqueuing
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system.mem_ctrls.readRowHits 642 # Number of row buffer hits during reads
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system.mem_ctrls.writeRowHits 873 # Number of row buffer hits during writes
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system.mem_ctrls.readRowHitRate 69.93 # Row buffer hit rate for reads
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system.mem_ctrls.writeRowHitRate 90.37 # Row buffer hit rate for writes
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system.mem_ctrls.avgGap 34.08 # Average gap between requests
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system.mem_ctrls.pageHitRate 80.41 # Row buffer hit rate, read and write combined
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system.mem_ctrls_0.actEnergy 491400 # Energy for activate commands per rank (pJ)
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system.mem_ctrls_0.preEnergy 273000 # Energy for precharge commands per rank (pJ)
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system.mem_ctrls_0.readEnergy 1547520 # Energy for read commands per rank (pJ)
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system.mem_ctrls_0.writeEnergy 1099008 # Energy for write commands per rank (pJ)
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system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
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system.mem_ctrls_0.actBackEnergy 55680336 # Energy for active background per rank (pJ)
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system.mem_ctrls_0.preBackEnergy 7372800 # Energy for precharge background per rank (pJ)
|
|
system.mem_ctrls_0.totalEnergy 72566784 # Total energy per rank (pJ)
|
|
system.mem_ctrls_0.averagePower 774.524869 # Core power per rank (mW)
|
|
system.mem_ctrls_0.memoryStateTime::IDLE 11950 # Time in different power states
|
|
system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states
|
|
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.mem_ctrls_0.memoryStateTime::ACT 78690 # Time in different power states
|
|
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.mem_ctrls_1.actEnergy 1882440 # Energy for activate commands per rank (pJ)
|
|
system.mem_ctrls_1.preEnergy 1045800 # Energy for precharge commands per rank (pJ)
|
|
system.mem_ctrls_1.readEnergy 9247680 # Energy for read commands per rank (pJ)
|
|
system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ)
|
|
system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
|
|
system.mem_ctrls_1.actBackEnergy 63740592 # Energy for active background per rank (pJ)
|
|
system.mem_ctrls_1.preBackEnergy 302400 # Energy for precharge background per rank (pJ)
|
|
system.mem_ctrls_1.totalEnergy 90315360 # Total energy per rank (pJ)
|
|
system.mem_ctrls_1.averagePower 963.960210 # Core power per rank (mW)
|
|
system.mem_ctrls_1.memoryStateTime::IDLE 182 # Time in different power states
|
|
system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states
|
|
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.mem_ctrls_1.memoryStateTime::ACT 90404 # Time in different power states
|
|
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 7 # Number of system calls
|
|
system.cpu.pwrStateResidencyTicks::ON 100232 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 100232 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 5641 # Number of instructions committed
|
|
system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
|
system.cpu.num_func_calls 191 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 4957 # number of integer instructions
|
|
system.cpu.num_fp_insts 2 # number of float instructions
|
|
system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
|
system.cpu.num_mem_refs 2037 # number of memory refs
|
|
system.cpu.num_load_insts 1135 # Number of load instructions
|
|
system.cpu.num_store_insts 902 # Number of store instructions
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 100232 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu.Branches 886 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 5642 # Class of executed instruction
|
|
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
|
system.ruby.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
|
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
|
system.ruby.delayHist::samples 2940 # delay histogram for all message
|
|
system.ruby.delayHist | 2940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
|
system.ruby.delayHist::total 2940 # delay histogram for all message
|
|
system.ruby.outstanding_req_hist_seqr::bucket_size 1
|
|
system.ruby.outstanding_req_hist_seqr::max_bucket 9
|
|
system.ruby.outstanding_req_hist_seqr::samples 7679
|
|
system.ruby.outstanding_req_hist_seqr::mean 1
|
|
system.ruby.outstanding_req_hist_seqr::gmean 1
|
|
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7679 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.outstanding_req_hist_seqr::total 7679
|
|
system.ruby.latency_hist_seqr::bucket_size 64
|
|
system.ruby.latency_hist_seqr::max_bucket 639
|
|
system.ruby.latency_hist_seqr::samples 7678
|
|
system.ruby.latency_hist_seqr::mean 12.054441
|
|
system.ruby.latency_hist_seqr::gmean 2.136034
|
|
system.ruby.latency_hist_seqr::stdev 27.599754
|
|
system.ruby.latency_hist_seqr | 7372 96.01% 96.01% | 253 3.30% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 6 0.08% 99.92% | 5 0.07% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.latency_hist_seqr::total 7678
|
|
system.ruby.hit_latency_hist_seqr::bucket_size 1
|
|
system.ruby.hit_latency_hist_seqr::max_bucket 9
|
|
system.ruby.hit_latency_hist_seqr::samples 6206
|
|
system.ruby.hit_latency_hist_seqr::mean 1
|
|
system.ruby.hit_latency_hist_seqr::gmean 1
|
|
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.hit_latency_hist_seqr::total 6206
|
|
system.ruby.miss_latency_hist_seqr::bucket_size 64
|
|
system.ruby.miss_latency_hist_seqr::max_bucket 639
|
|
system.ruby.miss_latency_hist_seqr::samples 1472
|
|
system.ruby.miss_latency_hist_seqr::mean 58.660326
|
|
system.ruby.miss_latency_hist_seqr::gmean 52.389786
|
|
system.ruby.miss_latency_hist_seqr::stdev 35.865583
|
|
system.ruby.miss_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.miss_latency_hist_seqr::total 1472
|
|
system.ruby.Directory.incomplete_times_seqr 1471
|
|
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits
|
|
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses
|
|
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses
|
|
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
|
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.ruby.network.routers0.percent_links_utilized 7.332987
|
|
system.ruby.network.routers0.msg_count.Control::2 1472
|
|
system.ruby.network.routers0.msg_count.Data::2 1468
|
|
system.ruby.network.routers0.msg_count.Response_Data::4 1472
|
|
system.ruby.network.routers0.msg_count.Writeback_Control::3 1468
|
|
system.ruby.network.routers0.msg_bytes.Control::2 11776
|
|
system.ruby.network.routers0.msg_bytes.Data::2 105696
|
|
system.ruby.network.routers0.msg_bytes.Response_Data::4 105984
|
|
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744
|
|
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.ruby.network.routers1.percent_links_utilized 7.332987
|
|
system.ruby.network.routers1.msg_count.Control::2 1472
|
|
system.ruby.network.routers1.msg_count.Data::2 1468
|
|
system.ruby.network.routers1.msg_count.Response_Data::4 1472
|
|
system.ruby.network.routers1.msg_count.Writeback_Control::3 1468
|
|
system.ruby.network.routers1.msg_bytes.Control::2 11776
|
|
system.ruby.network.routers1.msg_bytes.Data::2 105696
|
|
system.ruby.network.routers1.msg_bytes.Response_Data::4 105984
|
|
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744
|
|
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.ruby.network.routers2.percent_links_utilized 7.332987
|
|
system.ruby.network.routers2.msg_count.Control::2 1472
|
|
system.ruby.network.routers2.msg_count.Data::2 1468
|
|
system.ruby.network.routers2.msg_count.Response_Data::4 1472
|
|
system.ruby.network.routers2.msg_count.Writeback_Control::3 1468
|
|
system.ruby.network.routers2.msg_bytes.Control::2 11776
|
|
system.ruby.network.routers2.msg_bytes.Data::2 105696
|
|
system.ruby.network.routers2.msg_bytes.Response_Data::4 105984
|
|
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744
|
|
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.ruby.network.msg_count.Control 4416
|
|
system.ruby.network.msg_count.Data 4404
|
|
system.ruby.network.msg_count.Response_Data 4416
|
|
system.ruby.network.msg_count.Writeback_Control 4404
|
|
system.ruby.network.msg_byte.Control 35328
|
|
system.ruby.network.msg_byte.Data 317088
|
|
system.ruby.network.msg_byte.Response_Data 317952
|
|
system.ruby.network.msg_byte.Writeback_Control 35232
|
|
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
|
|
system.ruby.network.routers0.throttle0.link_utilization 7.340969
|
|
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472
|
|
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468
|
|
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105984
|
|
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11744
|
|
system.ruby.network.routers0.throttle1.link_utilization 7.325006
|
|
system.ruby.network.routers0.throttle1.msg_count.Control::2 1472
|
|
system.ruby.network.routers0.throttle1.msg_count.Data::2 1468
|
|
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11776
|
|
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105696
|
|
system.ruby.network.routers1.throttle0.link_utilization 7.325006
|
|
system.ruby.network.routers1.throttle0.msg_count.Control::2 1472
|
|
system.ruby.network.routers1.throttle0.msg_count.Data::2 1468
|
|
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11776
|
|
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105696
|
|
system.ruby.network.routers1.throttle1.link_utilization 7.340969
|
|
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1472
|
|
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1468
|
|
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105984
|
|
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11744
|
|
system.ruby.network.routers2.throttle0.link_utilization 7.340969
|
|
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1472
|
|
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1468
|
|
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105984
|
|
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11744
|
|
system.ruby.network.routers2.throttle1.link_utilization 7.325006
|
|
system.ruby.network.routers2.throttle1.msg_count.Control::2 1472
|
|
system.ruby.network.routers2.throttle1.msg_count.Data::2 1468
|
|
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11776
|
|
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105696
|
|
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
|
|
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
|
|
system.ruby.delayVCHist.vnet_1::samples 1472 # delay histogram for vnet_1
|
|
system.ruby.delayVCHist.vnet_1 | 1472 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
|
system.ruby.delayVCHist.vnet_1::total 1472 # delay histogram for vnet_1
|
|
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
|
|
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
|
|
system.ruby.delayVCHist.vnet_2::samples 1468 # delay histogram for vnet_2
|
|
system.ruby.delayVCHist.vnet_2 | 1468 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
|
system.ruby.delayVCHist.vnet_2::total 1468 # delay histogram for vnet_2
|
|
system.ruby.LD.latency_hist_seqr::bucket_size 64
|
|
system.ruby.LD.latency_hist_seqr::max_bucket 639
|
|
system.ruby.LD.latency_hist_seqr::samples 1135
|
|
system.ruby.LD.latency_hist_seqr::mean 33.525991
|
|
system.ruby.LD.latency_hist_seqr::gmean 10.018050
|
|
system.ruby.LD.latency_hist_seqr::stdev 38.312060
|
|
system.ruby.LD.latency_hist_seqr | 999 88.02% 88.02% | 116 10.22% 98.24% | 13 1.15% 99.38% | 0 0.00% 99.38% | 6 0.53% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.latency_hist_seqr::total 1135
|
|
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
|
|
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
|
|
system.ruby.LD.hit_latency_hist_seqr::samples 466
|
|
system.ruby.LD.hit_latency_hist_seqr::mean 1
|
|
system.ruby.LD.hit_latency_hist_seqr::gmean 1
|
|
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.hit_latency_hist_seqr::total 466
|
|
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
|
|
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
|
|
system.ruby.LD.miss_latency_hist_seqr::samples 669
|
|
system.ruby.LD.miss_latency_hist_seqr::mean 56.182362
|
|
system.ruby.LD.miss_latency_hist_seqr::gmean 49.875907
|
|
system.ruby.LD.miss_latency_hist_seqr::stdev 35.208867
|
|
system.ruby.LD.miss_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.miss_latency_hist_seqr::total 669
|
|
system.ruby.ST.latency_hist_seqr::bucket_size 64
|
|
system.ruby.ST.latency_hist_seqr::max_bucket 639
|
|
system.ruby.ST.latency_hist_seqr::samples 901
|
|
system.ruby.ST.latency_hist_seqr::mean 13.069922
|
|
system.ruby.ST.latency_hist_seqr::gmean 2.509564
|
|
system.ruby.ST.latency_hist_seqr::stdev 28.093942
|
|
system.ruby.ST.latency_hist_seqr | 870 96.56% 96.56% | 27 3.00% 99.56% | 3 0.33% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.latency_hist_seqr::total 901
|
|
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
|
|
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
|
|
system.ruby.ST.hit_latency_hist_seqr::samples 684
|
|
system.ruby.ST.hit_latency_hist_seqr::mean 1
|
|
system.ruby.ST.hit_latency_hist_seqr::gmean 1
|
|
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.hit_latency_hist_seqr::total 684
|
|
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
|
|
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
|
|
system.ruby.ST.miss_latency_hist_seqr::samples 217
|
|
system.ruby.ST.miss_latency_hist_seqr::mean 51.115207
|
|
system.ruby.ST.miss_latency_hist_seqr::gmean 45.620625
|
|
system.ruby.ST.miss_latency_hist_seqr::stdev 37.056021
|
|
system.ruby.ST.miss_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.miss_latency_hist_seqr::total 217
|
|
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
|
|
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
|
|
system.ruby.IFETCH.latency_hist_seqr::samples 5642
|
|
system.ruby.IFETCH.latency_hist_seqr::mean 7.572847
|
|
system.ruby.IFETCH.latency_hist_seqr::gmean 1.525495
|
|
system.ruby.IFETCH.latency_hist_seqr::stdev 22.420339
|
|
system.ruby.IFETCH.latency_hist_seqr | 5503 97.54% 97.54% | 110 1.95% 99.49% | 21 0.37% 99.86% | 4 0.07% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.latency_hist_seqr::total 5642
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5056
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
|
|
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5056 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::total 5056
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::samples 586
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.283276
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.328027
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.386051
|
|
system.ruby.IFETCH.miss_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::total 586
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1472
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.660326
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.389786
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.865583
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1472
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 669
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.182362
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.875907
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.208867
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 669
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 217
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 51.115207
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 45.620625
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 37.056021
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 217
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 586
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.283276
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.328027
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.386051
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 586
|
|
system.ruby.Directory_Controller.GETX 1472 0.00% 0.00%
|
|
system.ruby.Directory_Controller.PUTX 1468 0.00% 0.00%
|
|
system.ruby.Directory_Controller.Memory_Data 1472 0.00% 0.00%
|
|
system.ruby.Directory_Controller.Memory_Ack 1468 0.00% 0.00%
|
|
system.ruby.Directory_Controller.I.GETX 1472 0.00% 0.00%
|
|
system.ruby.Directory_Controller.M.PUTX 1468 0.00% 0.00%
|
|
system.ruby.Directory_Controller.IM.Memory_Data 1472 0.00% 0.00%
|
|
system.ruby.Directory_Controller.MI.Memory_Ack 1468 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Load 1135 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Ifetch 5642 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Store 901 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Data 1472 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Replacement 1468 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.Writeback_Ack 1468 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.I.Load 669 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.I.Ifetch 586 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.I.Store 217 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.Load 466 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.Ifetch 5056 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.Store 684 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.M.Replacement 1468 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1468 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.IS.Data 1255 0.00% 0.00%
|
|
system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00%
|
|
|
|
---------- End Simulation Statistics ----------
|