145 lines
4.4 KiB
Python
145 lines
4.4 KiB
Python
# Copyright (c) 2016 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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# Gabor Dozsa
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# System components used by the bigLITTLE.py configuration script
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import m5
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from m5.objects import *
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m5.util.addToPath('../../common')
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from Caches import *
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class L1I(L1_ICache):
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hit_latency = 1
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response_latency = 1
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mshrs = 4
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tgts_per_mshr = 8
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size = '48kB'
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assoc = 3
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class L1D(L1_DCache):
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hit_latency = 2
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response_latency = 1
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mshrs = 16
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tgts_per_mshr = 16
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size = '32kB'
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assoc = 2
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write_buffers = 16
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class WalkCache(PageTableWalkerCache):
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hit_latency = 4
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response_latency = 4
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mshrs = 6
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tgts_per_mshr = 8
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size = '1kB'
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assoc = 8
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write_buffers = 16
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class L2(L2Cache):
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hit_latency = 12
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response_latency = 5
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mshrs = 32
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tgts_per_mshr = 8
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size = '1MB'
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assoc = 16
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write_buffers = 8
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clusivity='mostly_excl'
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class L3(Cache):
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size = '16MB'
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assoc = 16
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hit_latency = 20
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response_latency = 20
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mshrs = 20
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tgts_per_mshr = 12
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clusivity='mostly_excl'
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class MemBus(SystemXBar):
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badaddr_responder = BadAddr(warn_access="warn")
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default = Self.badaddr_responder.pio
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class SimpleSystem(LinuxArmSystem):
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cache_line_size = 64
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voltage_domain = VoltageDomain(voltage="1.0V")
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clk_domain = SrcClockDomain(clock="1GHz",
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voltage_domain=Parent.voltage_domain)
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realview = VExpress_GEM5_V1()
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gic_cpu_addr = realview.gic.cpu_addr
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flags_addr = realview.realview_io.pio_addr + 0x30
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membus = MemBus()
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intrctrl = IntrControl()
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terminal = Terminal()
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vncserver = VncServer()
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iobus = IOXBar()
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# CPUs->PIO
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iobridge = Bridge(delay='50ns')
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# Device DMA -> MEM
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dmabridge = Bridge(delay='50ns', ranges=realview._mem_regions)
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_pci_devices = 0
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_clusters = []
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_cpus = []
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def attach_pci(self, dev):
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dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
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self._pci_devices += 1
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self.realview.attachPciDevice(dev, self.iobus)
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def connect(self):
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self.iobridge.master = self.iobus.slave
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self.iobridge.slave = self.membus.master
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self.dmabridge.master = self.membus.slave
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self.dmabridge.slave = self.iobus.master
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.realview.attachOnChipIO(self.membus, self.iobridge)
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self.realview.attachIO(self.iobus)
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self.system_port = self.membus.slave
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