892 lines
40 KiB
Plaintext
892 lines
40 KiB
Plaintext
// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Ali Saidi
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// Gabe Black
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// Steve Reinhardt
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////////////////////////////////////////////////////////////////////
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//
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// The actual decoder specification
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//
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decode OP default Unknown::unknown()
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{
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0x0: decode OP2
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{
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//Throw an illegal instruction acception
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0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
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format BranchN
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{
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0x1: decode BPCC
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{
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0x0: bpcci(19, {{
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if(passesCondition(Ccr<3:0>, COND2))
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x2: bpccx(19, {{
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if(passesCondition(Ccr<7:4>, COND2))
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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}
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0x2: bicc(22, {{
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if(passesCondition(Ccr<3:0>, COND2))
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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}
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0x3: decode RCOND2
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{
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format BranchSplit
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{
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0x1: bpreq({{
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if(Rs1.sdw == 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x2: bprle({{
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if(Rs1.sdw <= 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x3: bprl({{
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if(Rs1.sdw < 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x5: bprne({{
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if(Rs1.sdw != 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x6: bprg({{
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if(Rs1.sdw > 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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0x7: bprge({{
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if(Rs1.sdw >= 0)
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NNPC = xc->readPC() + disp;
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else
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handle_annul
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}});
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}
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}
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//SETHI (or NOP if rd == 0 and imm == 0)
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0x4: SetHi::sethi({{Rd = imm;}});
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0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
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0x6: Trap::fbfcc({{fault = new FpDisabled;}});
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}
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0x1: BranchN::call(30, {{
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R15 = xc->readPC();
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NNPC = R15 + disp;
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}});
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0x2: decode OP3 {
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format IntOp {
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0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
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0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
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0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
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0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
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0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
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0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
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0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
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0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
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0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
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0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
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0x0A: umul({{
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Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
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Y = Rd<63:32>;
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}});
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0x0B: smul({{
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Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
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Y = Rd.sdw;
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}});
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0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
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0x0D: udivx({{
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if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
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else Rd.udw = Rs1.udw / Rs2_or_imm13;
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}});
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0x0E: udiv({{
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if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
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else
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{
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Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
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if(Rd.udw >> 32 != 0)
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Rd.udw = 0xFFFFFFFF;
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}
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}});
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0x0F: sdiv({{
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if(Rs2_or_imm13.sdw == 0)
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fault = new DivisionByZero;
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else
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{
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Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
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if(Rd.udw<63:31> != 0)
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Rd.udw = 0x7FFFFFFF;
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else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
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Rd.udw = 0xFFFFFFFF80000000ULL;
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}
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}});
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}
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format IntOpCc {
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0x10: addcc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1 + val2;}},
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{{(Rs1<31:0> + val2<31:0>)<32:>}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
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0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
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0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
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0x14: subcc({{
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int64_t val2 = Rs2_or_imm13;
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Rd = Rs1 - val2;}},
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{{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
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{{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
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{{(~(Rs1<63:1> + (~val2)<63:1> +
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(Rs1 | ~val2)<0:>))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
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);
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0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
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0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
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0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
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0x18: addccc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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int64_t carryin = Ccr<0:0>;
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Rd = resTemp = Rs1 + val2 + carryin;}},
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{{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{(Rs1<63:1> + val2<63:1> +
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((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x1A: umulcc({{
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uint64_t resTemp;
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Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
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Y = resTemp<63:32>;}},
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{{0}},{{0}},{{0}},{{0}});
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0x1B: smulcc({{
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int64_t resTemp;
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Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
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Y = resTemp<63:32>;}},
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{{0}},{{0}},{{0}},{{0}});
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0x1C: subccc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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int64_t carryin = Ccr<0:0>;
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Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
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{{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
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{{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
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);
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0x1D: udivxcc({{
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if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
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else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
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,{{0}},{{0}},{{0}},{{0}});
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0x1E: udivcc({{
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uint32_t resTemp, val2 = Rs2_or_imm13.udw;
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int32_t overflow = 0;
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if(val2 == 0) fault = new DivisionByZero;
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else
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{
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resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
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overflow = (resTemp<63:32> != 0);
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if(overflow) Rd = resTemp = 0xFFFFFFFF;
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else Rd = resTemp;
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} }},
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{{0}},
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{{overflow}},
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{{0}},
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{{0}}
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);
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0x1F: sdivcc({{
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int64_t val2 = Rs2_or_imm13.sdw<31:0>;
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bool overflow = false, underflow = false;
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if(val2 == 0) fault = new DivisionByZero;
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else
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{
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Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
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overflow = (Rd<63:31> != 0);
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underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
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if(overflow) Rd = 0x7FFFFFFF;
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else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
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} }},
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{{0}},
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{{overflow || underflow}},
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{{0}},
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{{0}}
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);
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0x20: taddcc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x21: tsubcc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
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{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x22: taddcctv({{
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int64_t val2 = Rs2_or_imm13;
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Rd = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> ||
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(Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
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if(overflow) fault = new TagOverflow;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
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);
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0x23: tsubcctv({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
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if(overflow) fault = new TagOverflow;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x24: mulscc({{
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int64_t resTemp, multiplicand = Rs2_or_imm13;
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int32_t multiplier = Rs1<31:0>;
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int32_t savedLSB = Rs1<0:>;
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multiplier = multiplier<31:1> |
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((Ccr<3:3>
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^ Ccr<1:1>) << 32);
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if(!Y<0:>)
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multiplicand = 0;
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Rd = resTemp = multiplicand + multiplier;
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Y = Y<31:1> | (savedLSB << 31);}},
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{{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
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{{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
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{{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
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{{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
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);
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}
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format IntOp
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{
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0x25: decode X {
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0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
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0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
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}
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0x26: decode X {
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0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
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0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
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}
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0x27: decode X {
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0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
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0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
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}
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// XXX might want a format rdipr thing here
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0x28: decode RS1 {
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0xF: decode I {
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0x0: Nop::stbar({{/*stuff*/}});
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0x1: Nop::membar({{/*stuff*/}});
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}
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default: rdasr({{
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Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
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}});
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}
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0x29: HPriv::rdhpr({{
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// XXX Need to protect with format that traps non-priv/priv
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// access
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Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
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}});
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0x2A: Priv::rdpr({{
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// XXX Need to protect with format that traps non-priv
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// access
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Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
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}});
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0x2B: BasicOperate::flushw({{
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if(NWindows - 2 - Cansave == 0)
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{
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if(Otherwin)
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fault = new SpillNOther(Wstate<5:3>);
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else
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fault = new SpillNNormal(Wstate<2:0>);
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}
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}});
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0x2C: decode MOVCC3
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{
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0x0: Trap::movccfcc({{fault = new FpDisabled;}});
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0x1: decode CC
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{
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0x0: movcci({{
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if(passesCondition(Ccr<3:0>, COND4))
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Rd = Rs2_or_imm11;
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else
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Rd = Rd;
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}});
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0x2: movccx({{
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if(passesCondition(Ccr<7:4>, COND4))
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Rd = Rs2_or_imm11;
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else
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Rd = Rd;
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}});
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}
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}
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0x2D: sdivx({{
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if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
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else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
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}});
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0x2E: decode RS1 {
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0x0: IntOp::popc({{
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int64_t count = 0;
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uint64_t temp = Rs2_or_imm13;
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//Count the 1s in the front 4bits until none are left
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uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
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while(temp)
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{
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count += oneBits[temp & 0xF];
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temp = temp >> 4;
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}
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Rd = count;
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}});
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}
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0x2F: decode RCOND3
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{
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0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
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0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
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0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
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0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
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0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
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0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
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}
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0x30: wrasr({{
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xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x31: decode FCN {
|
|
0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
|
|
0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
|
|
}
|
|
0x32: Priv::wrpr({{
|
|
// XXX Need to protect with format that traps non-priv
|
|
// access
|
|
fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x33: HPriv::wrhpr({{
|
|
// XXX Need to protect with format that traps non-priv/priv
|
|
// access
|
|
fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x34: decode OPF{
|
|
format BasicOperate{
|
|
0x01: fmovs({{
|
|
Frd.sf = Frs2.sf;
|
|
//fsr.ftt = fsr.cexc = 0
|
|
Fsr &= ~(7 << 14);
|
|
Fsr &= ~(0x1F);
|
|
}});
|
|
0x02: fmovd({{
|
|
Frd.df = Frs2.df;
|
|
//fsr.ftt = fsr.cexc = 0
|
|
Fsr &= ~(7 << 14);
|
|
Fsr &= ~(0x1F);
|
|
}});
|
|
0x03: Trap::fmovq({{fault = new FpDisabled;}});
|
|
0x05: fnegs({{
|
|
//XXX might want to explicitly flip the sign bit
|
|
//So cases with Nan and +/-0 don't do weird things
|
|
Frd.sf = -Frs2.sf;
|
|
//fsr.ftt = fsr.cexc = 0
|
|
Fsr &= ~(7 << 14);
|
|
Fsr &= ~(0x1F);
|
|
}});
|
|
0x06: fnegd({{
|
|
//XXX might want to explicitly flip the sign bit
|
|
//So cases with Nan and +/-0 don't do weird things
|
|
Frd.df = -Frs2.df;
|
|
//fsr.ftt = fsr.cexc = 0
|
|
Fsr &= ~(7 << 14);
|
|
Fsr &= ~(0x1F);
|
|
}});
|
|
0x07: Trap::fnegq({{fault = new FpDisabled;}});
|
|
0x09: fabss({{
|
|
//XXX this instruction should be tested individually
|
|
//Clear the sign bit
|
|
Frd.sf = (float)(~(1 << 31) & ((uint32_t)Frs2.sf));
|
|
//fsr.ftt = fsr.cexc = 0
|
|
Fsr &= ~(7 << 14);
|
|
Fsr &= ~(0x1F);
|
|
}});
|
|
0x0A: fabsd({{
|
|
//XXX this instruction should be tested individually
|
|
//Clear the sign bit
|
|
Frd.df = (float)(~((uint64_t)1 << 63) & ((uint64_t)Frs2.df));
|
|
//fsr.ftt = fsr.cexc = 0
|
|
Fsr &= ~(7 << 14);
|
|
Fsr &= ~(0x1F);
|
|
}});
|
|
0x0B: Trap::fabsq({{fault = new FpDisabled;}});
|
|
0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}});
|
|
0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
|
|
0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
|
|
0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}});
|
|
0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
|
|
0x43: Trap::faddq({{fault = new FpDisabled;}});
|
|
0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}});
|
|
0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
|
|
0x47: Trap::fsubq({{fault = new FpDisabled;}});
|
|
0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}});
|
|
0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
|
|
0x4B: Trap::fmulq({{fault = new FpDisabled;}});
|
|
0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}});
|
|
0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
|
|
0x4F: Trap::fdivq({{fault = new FpDisabled;}});
|
|
0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}});
|
|
0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
|
|
0x81: fstox({{
|
|
Frd.df = (double)static_cast<int64_t>(Frs2.sf);
|
|
}});
|
|
0x82: fdtox({{
|
|
Frd.df = (double)static_cast<int64_t>(Frs2.df);
|
|
}});
|
|
0x83: Trap::fqtox({{fault = new FpDisabled;}});
|
|
0x84: fxtos({{
|
|
Frd.sf = static_cast<float>((int64_t)Frs2.df);
|
|
}});
|
|
0x88: fxtod({{
|
|
Frd.df = static_cast<double>((int64_t)Frs2.df);
|
|
}});
|
|
0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
|
|
0xC4: fitos({{
|
|
Frd.sf = static_cast<float>((int32_t)Frs2.sf);
|
|
}});
|
|
0xC6: fdtos({{Frd.sf = Frs2.df;}});
|
|
0xC7: Trap::fqtos({{fault = new FpDisabled;}});
|
|
0xC8: fitod({{
|
|
Frd.df = static_cast<double>((int32_t)Frs2.sf);
|
|
}});
|
|
0xC9: fstod({{Frd.df = Frs2.sf;}});
|
|
0xCB: Trap::fqtod({{fault = new FpDisabled;}});
|
|
0xCC: Trap::fitoq({{fault = new FpDisabled;}});
|
|
0xCD: Trap::fstoq({{fault = new FpDisabled;}});
|
|
0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
|
|
0xD1: fstoi({{
|
|
Frd.sf = (float)static_cast<int32_t>(Frs2.sf);
|
|
}});
|
|
0xD2: fdtoi({{
|
|
Frd.sf = (float)static_cast<int32_t>(Frs2.df);
|
|
}});
|
|
0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
|
|
default: Trap::fpop1({{fault = new FpDisabled;}});
|
|
}
|
|
}
|
|
0x35: Trap::fpop2({{fault = new FpDisabled;}});
|
|
//This used to be just impdep1, but now it's a whole bunch
|
|
//of instructions
|
|
0x36: decode OPF{
|
|
0x00: Trap::edge8({{fault = new IllegalInstruction;}});
|
|
0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
|
|
0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
|
|
0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
|
|
0x04: Trap::edge16({{fault = new IllegalInstruction;}});
|
|
0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
|
|
0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
|
|
0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
|
|
0x08: Trap::edge32({{fault = new IllegalInstruction;}});
|
|
0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
|
|
0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
|
|
0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
|
|
0x10: Trap::array8({{fault = new IllegalInstruction;}});
|
|
0x12: Trap::array16({{fault = new IllegalInstruction;}});
|
|
0x14: Trap::array32({{fault = new IllegalInstruction;}});
|
|
0x18: BasicOperate::alignaddress({{
|
|
uint64_t sum = Rs1 + Rs2;
|
|
Frd = sum & ~7;
|
|
Gsr = (Gsr & ~7) | (sum & 7);
|
|
}});
|
|
0x19: Trap::bmask({{fault = new IllegalInstruction;}});
|
|
0x1A: BasicOperate::alignaddresslittle({{
|
|
uint64_t sum = Rs1 + Rs2;
|
|
Frd = sum & ~7;
|
|
Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
|
|
}});
|
|
0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
|
|
0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
|
|
0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
|
|
0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
|
|
0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
|
|
0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
|
|
0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
|
|
0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
|
|
0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
|
|
0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
|
|
0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
|
|
0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
|
|
0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
|
|
0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
|
|
0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
|
|
0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
|
|
0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
|
|
0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
|
|
0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
|
|
0x48: BasicOperate::faligndata({{
|
|
uint64_t msbX = (uint64_t)Frs1;
|
|
uint64_t lsbX = (uint64_t)Frs2;
|
|
uint64_t msbShift = Gsr<2:0> * 8;
|
|
uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
|
|
uint64_t msbMask = ((uint64_t)(-1)) << msbShift;
|
|
uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
|
|
Frd = ((msbX << msbShift) & msbMask) |
|
|
((lsbX << lsbShift) & lsbMask);
|
|
}});
|
|
0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
|
|
0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
|
|
0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
|
|
0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
|
|
0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
|
|
0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
|
|
0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
|
|
0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
|
|
0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
|
|
0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
|
|
0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
|
|
0x60: BasicOperate::fzero({{Frd.df = 0;}});
|
|
0x61: BasicOperate::fzeros({{Frd.sf = 0;}});
|
|
0x62: Trap::fnor({{fault = new IllegalInstruction;}});
|
|
0x63: Trap::fnors({{fault = new IllegalInstruction;}});
|
|
0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
|
|
0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
|
|
0x66: BasicOperate::fnot2({{
|
|
Frd.df = (double)(~((uint64_t)Frs2.df));
|
|
}});
|
|
0x67: BasicOperate::fnot2s({{
|
|
Frd.sf = (float)(~((uint32_t)Frs2.sf));
|
|
}});
|
|
0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
|
|
0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
|
|
0x6A: BasicOperate::fnot1({{
|
|
Frd.df = (double)(~((uint64_t)Frs1.df));
|
|
}});
|
|
0x6B: BasicOperate::fnot1s({{
|
|
Frd.sf = (float)(~((uint32_t)Frs1.sf));
|
|
}});
|
|
0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
|
|
0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
|
|
0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
|
|
0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
|
|
0x70: Trap::fand({{fault = new IllegalInstruction;}});
|
|
0x71: Trap::fands({{fault = new IllegalInstruction;}});
|
|
0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
|
|
0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
|
|
0x74: BasicOperate::fsrc1({{Frd.df = Frs1.df;}});
|
|
0x75: BasicOperate::fsrc1s({{Frd.sf = Frs1.sf;}});
|
|
0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
|
|
0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
|
|
0x78: BasicOperate::fsrc2({{Frd.df = Frs2.df;}});
|
|
0x79: BasicOperate::fsrc2s({{Frd.sf = Frs2.sf;}});
|
|
0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
|
|
0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
|
|
0x7C: Trap::for({{fault = new IllegalInstruction;}});
|
|
0x7D: Trap::fors({{fault = new IllegalInstruction;}});
|
|
0x7E: Trap::fone({{fault = new IllegalInstruction;}});
|
|
0x7F: Trap::fones({{fault = new IllegalInstruction;}});
|
|
0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
|
|
0x81: Trap::siam({{fault = new IllegalInstruction;}});
|
|
}
|
|
0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
|
|
0x38: Branch::jmpl({{
|
|
Addr target = Rs1 + Rs2_or_imm13;
|
|
if(target & 0x3)
|
|
fault = new MemAddressNotAligned;
|
|
else
|
|
{
|
|
Rd = xc->readPC();
|
|
NNPC = target;
|
|
}
|
|
}});
|
|
0x39: Branch::return({{
|
|
//If both MemAddressNotAligned and
|
|
//a fill trap happen, it's not clear
|
|
//which one should be returned.
|
|
Addr target = Rs1 + Rs2_or_imm13;
|
|
if(target & 0x3)
|
|
fault = new MemAddressNotAligned;
|
|
else
|
|
NNPC = target;
|
|
if(fault == NoFault)
|
|
{
|
|
//CWP should be set directly so that it always happens
|
|
//Also, this will allow writing to the new window and
|
|
//reading from the old one
|
|
Cwp = (Cwp - 1 + NWindows) % NWindows;
|
|
if(Canrestore == 0)
|
|
{
|
|
if(Otherwin)
|
|
fault = new FillNOther(Wstate<5:3>);
|
|
else
|
|
fault = new FillNNormal(Wstate<2:0>);
|
|
}
|
|
else
|
|
{
|
|
Rd = Rs1 + Rs2_or_imm13;
|
|
Cansave = Cansave + 1;
|
|
Canrestore = Canrestore - 1;
|
|
}
|
|
//This is here to make sure the CWP is written
|
|
//no matter what. This ensures that the results
|
|
//are written in the new window as well.
|
|
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
|
|
}
|
|
}});
|
|
0x3A: decode CC
|
|
{
|
|
0x0: Trap::tcci({{
|
|
if(passesCondition(Ccr<3:0>, COND2))
|
|
{
|
|
int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
|
|
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
|
|
#if FULL_SYSTEM
|
|
fault = new TrapInstruction(lTrapNum);
|
|
#else
|
|
DPRINTF(Sparc, "The syscall number is %d\n", R1);
|
|
xc->syscall(R1);
|
|
#endif
|
|
}
|
|
}});
|
|
0x2: Trap::tccx({{
|
|
if(passesCondition(Ccr<7:4>, COND2))
|
|
{
|
|
int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
|
|
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
|
|
#if FULL_SYSTEM
|
|
fault = new TrapInstruction(lTrapNum);
|
|
#else
|
|
DPRINTF(Sparc, "The syscall number is %d\n", R1);
|
|
xc->syscall(R1);
|
|
#endif
|
|
}
|
|
}});
|
|
}
|
|
0x3B: Nop::flush({{/*Instruction memory flush*/}});
|
|
0x3C: save({{
|
|
//CWP should be set directly so that it always happens
|
|
//Also, this will allow writing to the new window and
|
|
//reading from the old one
|
|
if(Cansave == 0)
|
|
{
|
|
if(Otherwin)
|
|
fault = new SpillNOther(Wstate<5:3>);
|
|
else
|
|
fault = new SpillNNormal(Wstate<2:0>);
|
|
Cwp = (Cwp + 2) % NWindows;
|
|
}
|
|
else if(Cleanwin - Canrestore == 0)
|
|
{
|
|
Cwp = (Cwp + 1) % NWindows;
|
|
fault = new CleanWindow;
|
|
}
|
|
else
|
|
{
|
|
Cwp = (Cwp + 1) % NWindows;
|
|
Rd = Rs1 + Rs2_or_imm13;
|
|
Cansave = Cansave - 1;
|
|
Canrestore = Canrestore + 1;
|
|
}
|
|
//This is here to make sure the CWP is written
|
|
//no matter what. This ensures that the results
|
|
//are written in the new window as well.
|
|
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
|
|
}});
|
|
0x3D: restore({{
|
|
//CWP should be set directly so that it always happens
|
|
//Also, this will allow writing to the new window and
|
|
//reading from the old one
|
|
Cwp = (Cwp - 1 + NWindows) % NWindows;
|
|
if(Canrestore == 0)
|
|
{
|
|
if(Otherwin)
|
|
fault = new FillNOther(Wstate<5:3>);
|
|
else
|
|
fault = new FillNNormal(Wstate<2:0>);
|
|
}
|
|
else
|
|
{
|
|
Rd = Rs1 + Rs2_or_imm13;
|
|
Cansave = Cansave + 1;
|
|
Canrestore = Canrestore - 1;
|
|
}
|
|
//This is here to make sure the CWP is written
|
|
//no matter what. This ensures that the results
|
|
//are written in the new window as well.
|
|
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
|
|
}});
|
|
0x3E: decode FCN {
|
|
0x0: Priv::done({{
|
|
if(Tl == 0)
|
|
return new IllegalInstruction;
|
|
|
|
Cwp = Tstate<4:0>;
|
|
Pstate = Tstate<20:8>;
|
|
Asi = Tstate<31:24>;
|
|
Ccr = Tstate<39:32>;
|
|
Gl = Tstate<42:40>;
|
|
NPC = Tnpc;
|
|
NNPC = Tnpc + 4;
|
|
Tl = Tl - 1;
|
|
}});
|
|
0x1: Priv::retry({{
|
|
if(Tl == 0)
|
|
return new IllegalInstruction;
|
|
Cwp = Tstate<4:0>;
|
|
Pstate = Tstate<20:8>;
|
|
Asi = Tstate<31:24>;
|
|
Ccr = Tstate<39:32>;
|
|
Gl = Tstate<42:40>;
|
|
NPC = Tpc;
|
|
NNPC = Tnpc + 4;
|
|
Tl = Tl - 1;
|
|
}});
|
|
}
|
|
}
|
|
}
|
|
0x3: decode OP3 {
|
|
format Load {
|
|
0x00: lduw({{Rd = Mem;}}, {{32}});
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0x01: ldub({{Rd = Mem;}}, {{8}});
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0x02: lduh({{Rd = Mem;}}, {{16}});
|
|
0x03: ldd({{
|
|
uint64_t val = Mem;
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RdLow = val<31:0>;
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|
RdHigh = val<63:32>;
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|
}}, {{64}});
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}
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|
format Store {
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|
0x04: stw({{Mem = Rd.sw;}}, {{32}});
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0x05: stb({{Mem = Rd.sb;}}, {{8}});
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0x06: sth({{Mem = Rd.shw;}}, {{16}});
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|
0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
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}
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|
format Load {
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|
0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
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|
0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
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0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
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|
0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
|
|
0x0D: ldstub({{
|
|
Rd = Mem;
|
|
Mem = 0xFF;
|
|
}}, {{8}});
|
|
}
|
|
0x0E: Store::stx({{Mem = Rd}}, {{64}});
|
|
0x0F: LoadStore::swap({{
|
|
uint32_t temp = Rd;
|
|
Rd = Mem;
|
|
Mem = temp;
|
|
}}, {{32}});
|
|
format Load {
|
|
0x10: lduwa({{Rd = Mem;}}, {{32}});
|
|
0x11: lduba({{Rd = Mem;}}, {{8}});
|
|
0x12: lduha({{Rd = Mem;}}, {{16}});
|
|
0x13: ldda({{
|
|
uint64_t val = Mem;
|
|
RdLow = val<31:0>;
|
|
RdHigh = val<63:32>;
|
|
}}, {{64}});
|
|
}
|
|
format Store {
|
|
0x14: stwa({{Mem = Rd;}}, {{32}});
|
|
0x15: stba({{Mem = Rd;}}, {{8}});
|
|
0x16: stha({{Mem = Rd;}}, {{16}});
|
|
0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
|
|
}
|
|
format Load {
|
|
0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
|
|
0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
|
|
0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
|
|
0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
|
|
}
|
|
0x1D: LoadStore::ldstuba({{
|
|
Rd = Mem;
|
|
Mem = 0xFF;
|
|
}}, {{8}});
|
|
0x1E: Store::stxa({{Mem = Rd}}, {{64}});
|
|
0x1F: LoadStore::swapa({{
|
|
uint32_t temp = Rd;
|
|
Rd = Mem;
|
|
Mem = temp;
|
|
}}, {{32}});
|
|
format Trap {
|
|
0x20: Load::ldf({{Frd.sf = ((float)Mem);}}, {{32}});
|
|
0x21: decode X {
|
|
0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
|
|
0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
|
|
}
|
|
0x22: ldqf({{fault = new FpDisabled;}});
|
|
0x23: Load::lddf({{Frd.df = ((double)Mem);}}, {{64}});
|
|
0x24: Store::stf({{Mem = ((int32_t)Frd.sf);}}, {{32}});
|
|
0x25: decode X {
|
|
0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
|
|
0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
|
|
}
|
|
0x26: stqf({{fault = new FpDisabled;}});
|
|
0x27: Store::stdf({{Mem = ((int64_t)Frd.df);}}, {{64}});
|
|
0x2D: Nop::prefetch({{ }});
|
|
0x30: Load::ldfa({{Frd.sf = ((float)Mem);}}, {{32}});
|
|
0x32: ldqfa({{fault = new FpDisabled;}});
|
|
0x33: Load::lddfa({{Frd.df = ((double)Mem);}}, {{64}});
|
|
0x34: Store::stfa({{Mem = ((int32_t)Frd.sf);}}, {{32}});
|
|
0x36: stqfa({{fault = new FpDisabled;}});
|
|
//XXX need to work in the ASI thing
|
|
0x37: Store::stdfa({{Mem = ((uint64_t)Frd.df);}}, {{64}});
|
|
0x3C: Cas::casa({{
|
|
uint64_t val = Mem.uw;
|
|
if(Rs2.uw == val)
|
|
Mem.uw = Rd.uw;
|
|
Rd.uw = val;
|
|
}});
|
|
0x3D: Nop::prefetcha({{ }});
|
|
0x3E: Cas::casxa({{
|
|
uint64_t val = Mem.udw;
|
|
if(Rs2 == val)
|
|
Mem.udw = Rd;
|
|
Rd = val;
|
|
}});
|
|
}
|
|
}
|
|
}
|