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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
Andreas Hansson a217eba078 stats: Update stats for CPU and cache changes 
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
2014-09-03 07:42:59 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.962815 # Number of seconds simulated
sim_ticks 1962815218500 # Number of ticks simulated
final_tick 1962815218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1506000 # Simulator instruction rate (inst/s)
host_op_rate 1505999 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49787604582 # Simulator tick rate (ticks/s)
host_mem_usage 317424 # Number of bytes of host memory used
host_seconds 39.42 # Real time elapsed on the host
sim_insts 59372159 # Number of instructions simulated
sim_ops 59372159 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 724992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24166912 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 138560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1080576 # Number of bytes read from this memory
system.physmem.bytes_read::total 26112000 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 724992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 138560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5090112 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
system.physmem.bytes_written::total 7749440 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 11328 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 377608 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2165 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 16884 # Number of read requests responded to by this memory
system.physmem.num_reads::total 408000 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 79533 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
system.physmem.num_writes::total 121085 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 369363 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12312372 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 70592 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 550524 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13303341 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 369363 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 70592 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 439956 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2593271 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::tsunami.ide 1354854 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3948125 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2593271 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 369363 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12312372 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1355343 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 70592 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 550524 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17251466 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 408000 # Number of read requests accepted
system.physmem.writeReqs 121085 # Number of write requests accepted
system.physmem.readBursts 408000 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 121085 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 26099968 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue
system.physmem.bytesWritten 7747840 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 26112000 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7749440 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25223 # Per bank write bursts
system.physmem.perBankRdBursts::1 25569 # Per bank write bursts
system.physmem.perBankRdBursts::2 25254 # Per bank write bursts
system.physmem.perBankRdBursts::3 25702 # Per bank write bursts
system.physmem.perBankRdBursts::4 25695 # Per bank write bursts
system.physmem.perBankRdBursts::5 25237 # Per bank write bursts
system.physmem.perBankRdBursts::6 25154 # Per bank write bursts
system.physmem.perBankRdBursts::7 25289 # Per bank write bursts
system.physmem.perBankRdBursts::8 25197 # Per bank write bursts
system.physmem.perBankRdBursts::9 25673 # Per bank write bursts
system.physmem.perBankRdBursts::10 25761 # Per bank write bursts
system.physmem.perBankRdBursts::11 25821 # Per bank write bursts
system.physmem.perBankRdBursts::12 25887 # Per bank write bursts
system.physmem.perBankRdBursts::13 25811 # Per bank write bursts
system.physmem.perBankRdBursts::14 25568 # Per bank write bursts
system.physmem.perBankRdBursts::15 24971 # Per bank write bursts
system.physmem.perBankWrBursts::0 7862 # Per bank write bursts
system.physmem.perBankWrBursts::1 7635 # Per bank write bursts
system.physmem.perBankWrBursts::2 7481 # Per bank write bursts
system.physmem.perBankWrBursts::3 8078 # Per bank write bursts
system.physmem.perBankWrBursts::4 7635 # Per bank write bursts
system.physmem.perBankWrBursts::5 7244 # Per bank write bursts
system.physmem.perBankWrBursts::6 7160 # Per bank write bursts
system.physmem.perBankWrBursts::7 6937 # Per bank write bursts
system.physmem.perBankWrBursts::8 6882 # Per bank write bursts
system.physmem.perBankWrBursts::9 7297 # Per bank write bursts
system.physmem.perBankWrBursts::10 7429 # Per bank write bursts
system.physmem.perBankWrBursts::11 7398 # Per bank write bursts
system.physmem.perBankWrBursts::12 8124 # Per bank write bursts
system.physmem.perBankWrBursts::13 8265 # Per bank write bursts
system.physmem.perBankWrBursts::14 8169 # Per bank write bursts
system.physmem.perBankWrBursts::15 7464 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
system.physmem.totGap 1962808109000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 408000 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 121085 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 407738 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2710 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5918 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6075 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6272 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 7040 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7344 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8887 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8584 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8726 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6736 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5915 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5640 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 66023 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 512.666919 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 309.343673 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 413.043592 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 15664 23.73% 23.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11865 17.97% 41.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5137 7.78% 49.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3080 4.67% 54.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3330 5.04% 59.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1778 2.69% 61.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1463 2.22% 64.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1306 1.98% 66.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 22400 33.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 66023 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5447 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 74.865981 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2190.069327 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095 5442 99.91% 99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5447 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5447 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.225078 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 19.080270 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 19.855094 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 4780 87.75% 87.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 19 0.35% 88.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 16 0.29% 88.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 235 4.31% 92.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 38 0.70% 93.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 9 0.17% 93.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 13 0.24% 93.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 10 0.18% 94.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 23 0.42% 94.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 3 0.06% 94.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 2 0.04% 94.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 1 0.02% 94.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 7 0.13% 94.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.09% 94.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 4 0.07% 94.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 29 0.53% 95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 14 0.26% 95.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 6 0.11% 95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 6 0.11% 95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 182 3.34% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.04% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.04% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 10 0.18% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.04% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 5 0.09% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 5 0.09% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 8 0.15% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 2 0.04% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5447 # Writes before turning the bus around for reads
system.physmem.totQLat 2167934250 # Total ticks spent queuing
system.physmem.totMemAccLat 9814409250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2039060000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5316.01 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24066.01 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.30 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.13 # Data bus utilization in percentage
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing
system.physmem.readRowHits 365758 # Number of row buffer hits during reads
system.physmem.writeRowHits 97091 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.69 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.18 # Row buffer hit rate for writes
system.physmem.avgGap 3709816.21 # Average gap between requests
system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1840831671000 # Time in different power states
system.physmem.memoryStateTime::REF 65542620000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 56438386500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 17291736 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 292660 # Transaction distribution
system.membus.trans_dist::ReadResp 292660 # Transaction distribution
system.membus.trans_dist::WriteReq 12414 # Transaction distribution
system.membus.trans_dist::WriteResp 12414 # Transaction distribution
system.membus.trans_dist::Writeback 79533 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4556 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1019 # Transaction distribution
system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution
system.membus.trans_dist::ReadExReq 122803 # Transaction distribution
system.membus.trans_dist::ReadExResp 122701 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904540 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 943768 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83295 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83295 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1027063 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31201152 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 31269890 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 33930178 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 33930178 # Total data (bytes)
system.membus.snoop_data_through_bus 10304 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 39224500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1533573250 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 3826483141 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 43139750 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 342222 # number of replacements
system.l2c.tags.tagsinuse 65256.426750 # Cycle average of tags in use
system.l2c.tags.total_refs 2542307 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 407368 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 6.240812 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 8652281750 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 55518.260732 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3744.767678 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4299.632317 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1171.746225 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 522.019798 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.847141 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.057141 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.065607 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.017879 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.007965 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995734 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65146 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 748 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 5288 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7253 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 51739 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.994049 # Percentage of cache occupancy per task id
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system.l2c.tags.data_accesses 26946350 # Number of data accesses
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system.l2c.ReadReq_hits::cpu0.data 377901 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu1.data 449863 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1817000 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 850078 # number of Writeback hits
system.l2c.Writeback_hits::total 850078 # number of Writeback hits
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system.l2c.UpgradeReq_hits::cpu1.data 70 # number of UpgradeReq hits
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system.l2c.Writeback_accesses::writebacks 850078 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 850078 # number of Writeback accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::cpu1.data 101 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.overall_mshr_miss_latency::cpu1.inst 134094500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1024729765 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 22053134646 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 941946000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 449028500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1390974500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1618783500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 858261500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2477045000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2560729500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1307290000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 3868019500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.417395 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002333 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.135701 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.950694 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870130 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.937443 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.712644 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.792079 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755319 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.485366 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.157133 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.382340 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.434636 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.030627 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.168399 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.434636 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.030627 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.168399 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.993252 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 52912.555559 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001.767960 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.650716 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56070.797953 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60481.716729 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56639.797032 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 41699 # number of replacements
system.iocache.tags.tagsinuse 0.569942 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1756486320000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 0.569942 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.035621 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375552 # Number of tag accesses
system.iocache.tags.data_accesses 375552 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses
system.iocache.demand_misses::total 176 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 176 # number of overall misses
system.iocache.overall_misses::total 176 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles
system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 41552 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2504351556 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2504351556 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 6067147 # DTB read hits
system.cpu0.dtb.read_misses 7765 # DTB read misses
system.cpu0.dtb.read_acv 210 # DTB read access violations
system.cpu0.dtb.read_accesses 524069 # DTB read accesses
system.cpu0.dtb.write_hits 4265547 # DTB write hits
system.cpu0.dtb.write_misses 910 # DTB write misses
system.cpu0.dtb.write_acv 133 # DTB write access violations
system.cpu0.dtb.write_accesses 202595 # DTB write accesses
system.cpu0.dtb.data_hits 10332694 # DTB hits
system.cpu0.dtb.data_misses 8675 # DTB misses
system.cpu0.dtb.data_acv 343 # DTB access violations
system.cpu0.dtb.data_accesses 726664 # DTB accesses
system.cpu0.itb.fetch_hits 3354719 # ITB hits
system.cpu0.itb.fetch_misses 3984 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
system.cpu0.itb.fetch_accesses 3358703 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 3925630437 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 38276405 # Number of instructions committed
system.cpu0.committedOps 38276405 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 35596815 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 153493 # Number of float alu accesses
system.cpu0.num_func_calls 936479 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4465105 # number of instructions that are conditional controls
system.cpu0.num_int_insts 35596815 # number of integer instructions
system.cpu0.num_fp_insts 153493 # number of float instructions
system.cpu0.num_int_register_reads 48919188 # number of times the integer registers were read
system.cpu0.num_int_register_writes 26532196 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 75000 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 75910 # number of times the floating registers were written
system.cpu0.num_mem_refs 10365856 # number of memory refs
system.cpu0.num_load_insts 6090539 # Number of load instructions
system.cpu0.num_store_insts 4275317 # Number of store instructions
system.cpu0.num_idle_cycles 3742236660.998093 # Number of idle cycles
system.cpu0.num_busy_cycles 183393776.001907 # Number of busy cycles
system.cpu0.not_idle_fraction 0.046717 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.953283 # Percentage of idle cycles
system.cpu0.Branches 5694884 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2096297 5.48% 5.48% # Class of executed instruction
system.cpu0.op_class::IntAlu 24983670 65.26% 70.73% # Class of executed instruction
system.cpu0.op_class::IntMult 39322 0.10% 70.83% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 70.83% # Class of executed instruction
system.cpu0.op_class::FloatAdd 24596 0.06% 70.90% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::FloatDiv 1883 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction
system.cpu0.op_class::MemRead 6232893 16.28% 87.18% # Class of executed instruction
system.cpu0.op_class::MemWrite 4280562 11.18% 98.36% # Class of executed instruction
system.cpu0.op_class::IprAccess 626200 1.64% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 38285423 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 4863 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 138357 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 44808 38.76% 38.76% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 68665 59.40% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 115595 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 44283 48.84% 48.84% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 44267 48.82% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 90672 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1909699143000 97.29% 97.29% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 95243500 0.00% 97.30% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 764380500 0.04% 97.34% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 52243094000 2.66% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1962814446500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.988283 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.644681 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 234 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
system.cpu0.kern.callpal::swpctx 2216 1.80% 1.87% # number of callpals executed
system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed
system.cpu0.kern.callpal::swpipl 109456 88.95% 90.88% # number of callpals executed
system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed
system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.01% 96.30% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.30% # number of callpals executed
system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed
system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed
system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 123047 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5724 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1371
system.cpu0.kern.mode_good::user 1372
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.239518 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.386556 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1959023925000 99.81% 99.81% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 3790517000 0.19% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 2217 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.throughput 109416622 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2148133 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2148118 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 850078 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 41558 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 4615 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 1065 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 5680 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 322069 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 322069 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078328 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181300 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927173 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598235 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5785036 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34505856 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81606637 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29669504 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63812309 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 209594306 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 209584002 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 5180608 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 5075622491 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2428486244 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 4030575545 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 2086565739 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 2646502814 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
system.iobus.throughput 1391048 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7376 # Transaction distribution
system.iobus.trans_dist::ReadResp 7376 # Transaction distribution
system.iobus.trans_dist::WriteReq 53966 # Transaction distribution
system.iobus.trans_dist::WriteResp 53966 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10614 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 484 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 39228 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 122684 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42456 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1936 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 68738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2730370 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2730370 # Total data (bytes)
system.iobus.reqLayer0.occupancy 9969000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 362000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 374413689 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42018250 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.icache.tags.replacements 538541 # number of replacements
system.cpu0.icache.tags.tagsinuse 508.393356 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 37746250 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 539053 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 70.023263 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393356 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 38824598 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 38824598 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 37746250 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 37746250 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 37746250 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 37746250 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 37746250 # number of overall hits
system.cpu0.icache.overall_hits::total 37746250 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 539174 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 539174 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 539174 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 539174 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 539174 # number of overall misses
system.cpu0.icache.overall_misses::total 539174 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7756302744 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 7756302744 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 7756302744 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 7756302744 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 7756302744 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 7756302744 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285424 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 38285424 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 38285424 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 38285424 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 38285424 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 38285424 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014083 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014083 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014083 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014083 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014083 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014083 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14385.528130 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14385.528130 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14385.528130 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14385.528130 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539174 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 539174 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 539174 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 539174 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 539174 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 539174 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6673548256 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 6673548256 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6673548256 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 6673548256 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6673548256 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 6673548256 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014083 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014083 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014083 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12377.355466 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 871192 # number of replacements
system.cpu0.dcache.tags.tagsinuse 481.742326 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 9465806 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 871704 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 10.858968 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.742326 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940903 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.940903 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 42232679 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 42232679 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 5299779 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5299779 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3905718 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3905718 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 124794 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 124794 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 131579 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 131579 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 9205497 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 9205497 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 9205497 # number of overall hits
system.cpu0.dcache.overall_hits::total 9205497 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 645318 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 645318 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 224183 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 224183 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7829 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 7829 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 497 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 497 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 869501 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 869501 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 869501 # number of overall misses
system.cpu0.dcache.overall_misses::total 869501 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374202500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 23374202500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262527483 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 9262527483 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102834500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 102834500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3584562 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 3584562 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 32636729983 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 32636729983 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 32636729983 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 32636729983 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945097 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 5945097 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4129901 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4129901 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132623 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 132623 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132076 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 132076 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 10074998 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 10074998 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 10074998 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 10074998 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108546 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.108546 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054283 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.054283 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059032 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059032 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003763 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003763 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086303 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.086303 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086303 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.086303 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36221.215742 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 36221.215742 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41316.814758 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 41316.814758 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13135.074722 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13135.074722 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7212.398390 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7212.398390 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 37535.011441 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 405151 # number of writebacks
system.cpu0.dcache.writebacks::total 405151 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645318 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 645318 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224183 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 224183 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7829 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7829 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 497 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 497 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 869501 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 869501 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 869501 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 869501 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958327500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958327500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8765186517 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8765186517 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87163500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87163500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2590438 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2590438 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723514017 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 30723514017 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723514017 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 30723514017 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004927000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004927000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718158000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718158000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723085000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723085000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108546 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108546 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054283 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054283 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059032 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059032 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003763 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003763 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.086303 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.086303 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5212.148893 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5212.148893 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 3617054 # DTB read hits
system.cpu1.dtb.read_misses 2620 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 205337 # DTB read accesses
system.cpu1.dtb.write_hits 2433875 # DTB write hits
system.cpu1.dtb.write_misses 235 # DTB write misses
system.cpu1.dtb.write_acv 24 # DTB write access violations
system.cpu1.dtb.write_accesses 89739 # DTB write accesses
system.cpu1.dtb.data_hits 6050929 # DTB hits
system.cpu1.dtb.data_misses 2855 # DTB misses
system.cpu1.dtb.data_acv 24 # DTB access violations
system.cpu1.dtb.data_accesses 295076 # DTB accesses
system.cpu1.itb.fetch_hits 1988100 # ITB hits
system.cpu1.itb.fetch_misses 1064 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
system.cpu1.itb.fetch_accesses 1989164 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 3923841470 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 21095754 # Number of instructions committed
system.cpu1.committedOps 21095754 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 19410964 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses
system.cpu1.num_func_calls 648514 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 2286581 # number of instructions that are conditional controls
system.cpu1.num_int_insts 19410964 # number of integer instructions
system.cpu1.num_fp_insts 175175 # number of float instructions
system.cpu1.num_int_register_reads 26520307 # number of times the integer registers were read
system.cpu1.num_int_register_writes 14289908 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written
system.cpu1.num_mem_refs 6073169 # number of memory refs
system.cpu1.num_load_insts 3630901 # Number of load instructions
system.cpu1.num_store_insts 2442268 # Number of store instructions
system.cpu1.num_idle_cycles 3837673362.965370 # Number of idle cycles
system.cpu1.num_busy_cycles 86168107.034630 # Number of busy cycles
system.cpu1.not_idle_fraction 0.021960 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.978040 # Percentage of idle cycles
system.cpu1.Branches 3165037 # Number of branches fetched
system.cpu1.op_class::No_OpClass 1250062 5.92% 5.92% # Class of executed instruction
system.cpu1.op_class::IntAlu 13186802 62.50% 68.43% # Class of executed instruction
system.cpu1.op_class::IntMult 30198 0.14% 68.57% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction
system.cpu1.op_class::FloatAdd 13644 0.06% 68.63% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction
system.cpu1.op_class::FloatDiv 1759 0.01% 68.64% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction
system.cpu1.op_class::MemRead 3726078 17.66% 86.30% # Class of executed instruction
system.cpu1.op_class::MemWrite 2443288 11.58% 97.88% # Class of executed instruction
system.cpu1.op_class::IprAccess 446802 2.12% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 21098633 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 100733 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 37218 40.29% 40.29% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 53108 57.49% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 92382 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 36366 48.68% 48.68% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 36280 48.57% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 74702 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1906657223000 97.18% 97.18% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 706239500 0.04% 97.22% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 54497875500 2.78% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1961920705000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.683136 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.808621 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 92 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed
system.cpu1.kern.callpal::swpipl 87059 91.90% 94.06% # number of callpals executed
system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed
system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 96.38% # number of callpals executed
system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # number of callpals executed
system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed
system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 94732 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches
system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 415
system.cpu1.kern.mode_good::user 367
system.cpu1.kern.mode_good::idle 48
system.cpu1.kern.mode_switch_good::kernel 0.171843 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.172235 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 65779284000 3.35% 3.35% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1486343500 0.08% 3.43% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1893759051500 96.57% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 2021 # number of times the context was actually changed
system.cpu1.icache.tags.replacements 463035 # number of replacements
system.cpu1.icache.tags.tagsinuse 500.061178 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 20635046 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 463547 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 44.515542 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061178 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 21562220 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 21562220 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 20635046 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 20635046 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 20635046 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 20635046 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 20635046 # number of overall hits
system.cpu1.icache.overall_hits::total 20635046 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 463587 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 463587 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 463587 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 463587 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 463587 # number of overall misses
system.cpu1.icache.overall_misses::total 463587 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6202855739 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6202855739 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6202855739 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6202855739 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6202855739 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6202855739 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098633 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 21098633 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 21098633 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 21098633 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 21098633 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 21098633 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021972 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.021972 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021972 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.021972 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021972 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.021972 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13380.133047 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13380.133047 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13380.133047 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463587 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 463587 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 463587 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 463587 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 463587 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 463587 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5274833261 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5274833261 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5274833261 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5274833261 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5274833261 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5274833261 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021972 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.021972 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.021972 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 581700 # number of replacements
system.cpu1.dcache.tags.tagsinuse 492.027042 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 5462019 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 582040 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 9.384267 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027042 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960990 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.960990 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 340 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.664062 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 24828314 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 24828314 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 3080149 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 3080149 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 2259986 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 2259986 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60927 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 60927 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71555 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 71555 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 5340135 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 5340135 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 5340135 # number of overall hits
system.cpu1.dcache.overall_hits::total 5340135 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 473178 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 473178 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 102501 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 102501 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11671 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11671 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 568 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 568 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 575679 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 575679 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 575679 # number of overall misses
system.cpu1.dcache.overall_misses::total 575679 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938208750 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 5938208750 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2338814234 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 2338814234 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149892750 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 149892750 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4181580 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4181580 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 8277022984 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 8277022984 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 8277022984 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 8277022984 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553327 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 3553327 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362487 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 2362487 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72598 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 72598 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72123 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 72123 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 5915814 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 5915814 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 5915814 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 5915814 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133165 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.133165 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160762 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160762 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007875 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007875 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097312 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.097312 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097312 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.097312 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22817.477234 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22817.477234 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.179676 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.179676 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.936620 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.936620 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14377.844222 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14377.844222 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 444927 # number of writebacks
system.cpu1.dcache.writebacks::total 444927 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473178 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 473178 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102501 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 102501 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11671 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11671 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 568 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 568 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 575679 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 575679 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 575679 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 575679 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4991497250 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4991497250 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2127317766 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2127317766 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126550250 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126550250 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3045420 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3045420 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7118815016 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 7118815016 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7118815016 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 7118815016 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907862000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907862000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387520500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387520500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133165 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133165 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160762 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160762 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007875 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007875 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.097312 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.097312 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10548.878540 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20754.117189 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.136835 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.654930 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.654930 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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