a217eba078
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
726 lines
82 KiB
Plaintext
726 lines
82 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.537826 # Number of seconds simulated
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sim_ticks 537826498500 # Number of ticks simulated
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final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 114564 # Simulator instruction rate (inst/s)
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host_op_rate 141043 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 96175687 # Simulator tick rate (ticks/s)
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host_mem_usage 263048 # Number of bytes of host memory used
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host_seconds 5592.13 # Real time elapsed on the host
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sim_insts 640655084 # Number of instructions simulated
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sim_ops 788730743 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 18593984 # Number of bytes read from this memory
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system.physmem.bytes_read::total 18593984 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 165056 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 165056 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 290531 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 290531 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 34572458 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 34572458 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 306895 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 306895 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 7865496 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 7865496 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 7865496 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 34572458 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 42437954 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 290531 # Number of read requests accepted
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system.physmem.writeReqs 66098 # Number of write requests accepted
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system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 18283 # Per bank write bursts
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system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
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system.physmem.perBankRdBursts::2 18223 # Per bank write bursts
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system.physmem.perBankRdBursts::3 18187 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18258 # Per bank write bursts
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system.physmem.perBankRdBursts::5 18313 # Per bank write bursts
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system.physmem.perBankRdBursts::6 18090 # Per bank write bursts
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system.physmem.perBankRdBursts::7 17910 # Per bank write bursts
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system.physmem.perBankRdBursts::8 17943 # Per bank write bursts
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system.physmem.perBankRdBursts::9 17966 # Per bank write bursts
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system.physmem.perBankRdBursts::10 18023 # Per bank write bursts
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system.physmem.perBankRdBursts::11 18118 # Per bank write bursts
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system.physmem.perBankRdBursts::12 18159 # Per bank write bursts
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system.physmem.perBankRdBursts::13 18277 # Per bank write bursts
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system.physmem.perBankRdBursts::14 18081 # Per bank write bursts
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system.physmem.perBankRdBursts::15 18260 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4137 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4147 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4225 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4171 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4094 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 537826410500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 290531 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66098 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads
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system.physmem.totQLat 3341298000 # Total ticks spent queuing
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system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 7.87 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.33 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing
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system.physmem.readRowHits 194846 # Number of row buffer hits during reads
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system.physmem.writeRowHits 49995 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes
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system.physmem.avgGap 1508083.78 # Average gap between requests
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system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states
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system.physmem.memoryStateTime::REF 17958980000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.throughput 42437954 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 224439 # Transaction distribution
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system.membus.trans_dist::ReadResp 224439 # Transaction distribution
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system.membus.trans_dist::Writeback 66098 # Transaction distribution
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system.membus.trans_dist::ReadExReq 66092 # Transaction distribution
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system.membus.trans_dist::ReadExResp 66092 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 22824256 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
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system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 154837020 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 104970668 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 12892448 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 106220966 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 82647169 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 77.806832 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 19441660 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 1323 # Number of incorrect RAS predictions.
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 673 # Number of system calls
|
|
system.cpu.numCycles 1075652997 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 640655084 # Number of instructions committed
|
|
system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 25219021 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.678989 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.595596 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped
|
|
system.cpu.icache.tags.replacements 23597 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 580074571 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 580074571 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 289999264 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 289999264 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 289999264 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 289999264 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 289999264 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 289999264 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 25348 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 290024612 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 290024612 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 290024612 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.cpu.l2cache.tags.replacements 257750 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2831 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29389 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 7553321 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 7553321 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 513976 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 513976 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 517207 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 517207 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 517207 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 517207 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 224469 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 224469 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 66092 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66092 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 290561 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 290561 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69323 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 807768 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 807768 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 807768 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 807768 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.303975 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.303975 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953392 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953392 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 29 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 29 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 29 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224440 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 224440 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66092 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66092 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 290532 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 290532 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 290532 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 290532 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13902147000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13902147000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3594959250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3594959250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497106250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17497106250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497106250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17497106250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303936 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303936 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953392 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953392 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.359673 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 778324 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4092.650508 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 378453595 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 782420 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 483.696218 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 745524250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.650508 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1354 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1577 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 759392478 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 759392478 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.inst 249628224 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 249628224 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.inst 128813893 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 128813893 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.inst 378442117 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 378442117 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.inst 378442117 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 378442117 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.inst 713850 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 713850 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.inst 137584 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 137584 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.inst 851434 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 851434 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.inst 379293551 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 379293551 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.inst 379293551 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 379293551 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001067 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001067 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 91420 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 753 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 753 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68261 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 68261 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.inst 69014 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 69014 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.inst 69014 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 69014 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 713097 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 713097 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69323 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|