a217eba078
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
511 lines
57 KiB
Plaintext
511 lines
57 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.286250 # Number of seconds simulated
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sim_ticks 1286249820000 # Number of ticks simulated
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final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 839019 # Simulator instruction rate (inst/s)
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host_op_rate 839019 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1162182391 # Simulator tick rate (ticks/s)
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host_mem_usage 244120 # Number of bytes of host memory used
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host_seconds 1106.75 # Real time elapsed on the host
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sim_insts 928587629 # Number of instructions simulated
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sim_ops 928587629 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 18465664 # Number of bytes read from this memory
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system.physmem.bytes_read::total 18603456 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 288526 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 290679 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 107127 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 14356203 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 14463330 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 107127 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 107127 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3317950 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 3317950 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3317950 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 17781280 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 224031 # Transaction distribution
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system.membus.trans_dist::ReadResp 224031 # Transaction distribution
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system.membus.trans_dist::Writeback 66683 # Transaction distribution
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system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
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system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 22871168 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 237510597 # DTB read hits
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system.cpu.dtb.read_misses 194650 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 237705247 # DTB read accesses
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system.cpu.dtb.write_hits 98301200 # DTB write hits
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system.cpu.dtb.write_misses 6871 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 98308071 # DTB write accesses
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system.cpu.dtb.data_hits 335811797 # DTB hits
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system.cpu.dtb.data_misses 201521 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 336013318 # DTB accesses
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system.cpu.itb.fetch_hits 928789151 # ITB hits
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system.cpu.itb.fetch_misses 105 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 928789256 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 37 # Number of system calls
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system.cpu.numCycles 2572499640 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 928587629 # Number of instructions committed
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system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
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system.cpu.num_func_calls 37048314 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
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system.cpu.num_int_insts 822136244 # number of integer instructions
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system.cpu.num_fp_insts 33439365 # number of float instructions
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system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
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system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
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system.cpu.num_mem_refs 336013318 # number of memory refs
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system.cpu.num_load_insts 237705247 # Number of load instructions
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system.cpu.num_store_insts 98308071 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 2572499640 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 123111018 # Number of branches fetched
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system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
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system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
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system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
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system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
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system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
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system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
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system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
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system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction
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system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 928789150 # Class of executed instruction
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system.cpu.icache.tags.replacements 4618 # number of replacements
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system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id
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system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses
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system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses
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system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits
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system.cpu.icache.overall_hits::total 928782983 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses
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system.cpu.icache.overall_misses::total 6168 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 158274000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 158274000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 158274000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 158274000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 158274000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 158274000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25660.505837 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25660.505837 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 257900 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 32657.894031 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249737 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487767 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.996640 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1144 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31198 # Occupied blocks per task id
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system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id
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system.cpu.l2cache.tags.tag_accesses 7386496 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 7386496 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 4015 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 489636 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 493651 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 91660 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 91660 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 4015 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 492002 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 496017 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 4015 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 492002 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 496017 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2153 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 221878 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 224031 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2153 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 288526 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 290679 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 288526 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 290679 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111956000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11537659000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 11649615000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3465696000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3465696000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 15003355000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 15115311000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 15003355000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 15115311000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 91660 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 91660 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311839 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.312159 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.349060 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.369655 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.369493 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.013521 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.013391 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52000.010321 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52000.010321 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2153 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221878 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 224031 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 288526 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 290679 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8875123000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8961243000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2665920000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2665920000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11541043000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11627163000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11541043000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 11627163000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.013521 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.013391 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 776432 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4094.261324 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 1046536000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261324 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 335031269 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568561000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 18568561000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 22264959000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 22264959000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 22264959000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 22264959000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 28525.509655 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 91660 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
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|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 43704406 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 56214784 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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