a217eba078
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
188 lines
20 KiB
Text
188 lines
20 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.201717 # Number of seconds simulated
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sim_ticks 201717313500 # Number of ticks simulated
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final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1169681 # Simulator instruction rate (inst/s)
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host_op_rate 1404332 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 864148101 # Simulator tick rate (ticks/s)
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host_mem_usage 314684 # Number of bytes of host memory used
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host_seconds 233.43 # Real time elapsed on the host
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sim_insts 273037594 # Number of instructions simulated
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sim_ops 327811949 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 1394641092 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1875350308 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1394641092 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1394641092 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory
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system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 348660273 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 434960784 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 6913839312 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2383083572 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 9296922884 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 6913839312 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 6913839312 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1983209850 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1983209850 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 11280132734 # Throughput (bytes/s)
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system.membus.data_through_bus 2275398071 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 191 # Number of system calls
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system.cpu.numCycles 403434628 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 273037594 # Number of instructions committed
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system.cpu.committedOps 327811949 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
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system.cpu.num_func_calls 12448615 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls
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system.cpu.num_int_insts 258331481 # number of integer instructions
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system.cpu.num_fp_insts 114216705 # number of float instructions
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system.cpu.num_int_register_reads 1174407516 # number of times the integer registers were read
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system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
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system.cpu.num_cc_register_reads 985884623 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written
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system.cpu.num_mem_refs 168107829 # number of memory refs
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system.cpu.num_load_insts 85732235 # Number of load instructions
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system.cpu.num_store_insts 82375594 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 403434628 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 30563490 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 104312492 31.82% 31.82% # Class of executed instruction
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system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
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system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction
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system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 327812144 # Class of executed instruction
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---------- End Simulation Statistics ----------
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