a217eba078
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
1114 lines
127 KiB
Plaintext
1114 lines
127 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.195021 # Number of seconds simulated
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sim_ticks 195020773000 # Number of ticks simulated
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final_tick 195020773000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 105873 # Simulator instruction rate (inst/s)
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host_op_rate 114698 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 40866801 # Simulator tick rate (ticks/s)
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host_mem_usage 257276 # Number of bytes of host memory used
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host_seconds 4772.11 # Real time elapsed on the host
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sim_insts 505237723 # Number of instructions simulated
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sim_ops 547350944 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 207936 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9274560 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9482496 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 207936 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 207936 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6243584 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6243584 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 3249 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 144915 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 148164 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 97556 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 97556 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1066225 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 47556780 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 48623005 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1066225 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1066225 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 32014969 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 32014969 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 32014969 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1066225 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 47556780 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 80637974 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 148164 # Number of read requests accepted
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system.physmem.writeReqs 97556 # Number of write requests accepted
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system.physmem.readBursts 148164 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 97556 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 9474176 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6241856 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 9482496 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6243584 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 9585 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9250 # Per bank write bursts
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system.physmem.perBankRdBursts::2 9223 # Per bank write bursts
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system.physmem.perBankRdBursts::3 8986 # Per bank write bursts
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system.physmem.perBankRdBursts::4 9777 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9541 # Per bank write bursts
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system.physmem.perBankRdBursts::6 9063 # Per bank write bursts
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system.physmem.perBankRdBursts::7 8318 # Per bank write bursts
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system.physmem.perBankRdBursts::8 8791 # Per bank write bursts
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system.physmem.perBankRdBursts::9 8912 # Per bank write bursts
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system.physmem.perBankRdBursts::10 8928 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9775 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9650 # Per bank write bursts
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system.physmem.perBankRdBursts::13 9761 # Per bank write bursts
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system.physmem.perBankRdBursts::14 8979 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9495 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6258 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6150 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6073 # Per bank write bursts
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system.physmem.perBankWrBursts::3 5890 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6255 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6221 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6024 # Per bank write bursts
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system.physmem.perBankWrBursts::7 5542 # Per bank write bursts
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system.physmem.perBankWrBursts::8 5802 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5901 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5976 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6519 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6371 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6333 # Per bank write bursts
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system.physmem.perBankWrBursts::14 6062 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6152 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 195020664000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 148164 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 97556 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 137840 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 9554 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 574 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2105 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2265 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5823 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5839 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5855 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5867 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 5891 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5873 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5884 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5884 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5906 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5955 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5832 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 5848 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5868 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 21 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 65254 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 240.825329 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 153.977579 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 256.120796 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 26634 40.82% 40.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 17090 26.19% 67.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 6012 9.21% 76.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 6427 9.85% 86.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 3020 4.63% 90.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1342 2.06% 92.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 838 1.28% 94.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 692 1.06% 95.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 3199 4.90% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 65254 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5732 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 25.824669 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 376.283766 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 5727 99.91% 99.91% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5732 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5732 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.014829 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.919448 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 2.243342 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-17 3608 62.94% 62.94% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18-19 1943 33.90% 96.84% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20-21 77 1.34% 98.19% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22-23 32 0.56% 98.74% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24-25 17 0.30% 99.04% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::28-29 11 0.19% 99.56% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::30-31 3 0.05% 99.62% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32-33 2 0.03% 99.65% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::34-35 6 0.10% 99.76% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::36-37 2 0.03% 99.79% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::38-39 3 0.05% 99.84% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::40-41 2 0.03% 99.88% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::42-43 1 0.02% 99.90% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::50-51 3 0.05% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 5732 # Writes before turning the bus around for reads
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system.physmem.totQLat 1847546250 # Total ticks spent queuing
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system.physmem.totMemAccLat 4623183750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 740170000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 12480.55 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 31230.55 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 48.58 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 32.01 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 48.62 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 32.01 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.63 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.25 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 19.21 # Average write queue length when enqueuing
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system.physmem.readRowHits 116004 # Number of row buffer hits during reads
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system.physmem.writeRowHits 64298 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 78.36 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 65.91 # Row buffer hit rate for writes
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system.physmem.avgGap 793670.29 # Average gap between requests
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system.physmem.pageHitRate 73.42 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 115260013250 # Time in different power states
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|
system.physmem.memoryStateTime::REF 6511960000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 73245775250 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.membus.throughput 80637974 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 46897 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 46897 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 97556 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 9 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 101267 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 101267 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393902 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 393902 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15726080 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 15726080 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 15726080 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1079373000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1394503741 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 200189098 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 149602484 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 7338467 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 107397070 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 96034676 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 89.420201 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 14381720 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 112950 # Number of incorrect RAS predictions.
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
system.cpu.numCycles 390041547 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 129697358 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 835224616 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 200189098 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 110416396 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 251952283 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 16305676 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 725 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 125022986 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 2819221 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 389803312 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.324321 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.986703 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 204497213 52.46% 52.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 16740879 4.29% 56.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 25096143 6.44% 63.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 25406235 6.52% 69.71% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 22255484 5.71% 75.42% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 19361790 4.97% 80.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 11228649 2.88% 83.27% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 12061789 3.09% 86.36% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 53155130 13.64% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 389803312 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.513251 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.141373 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 103986680 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 118578898 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 144750042 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 14406980 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 8080712 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 27470111 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 74706 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 847095448 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 284101 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 8080712 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 110645607 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 38128402 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 58728570 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 152416718 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 21803303 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 812473012 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 12287 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 7169304 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 5481410 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 7159011 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 991790845 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3569028243 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 858899446 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 368 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 337667094 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 2298389 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 3025745 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 46474458 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 165564895 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 77029612 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 33913346 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 24718127 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 764294822 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 3785962 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 654447179 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 456586 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 218477687 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 578622397 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 808330 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 389803312 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.678916 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.824028 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 146772690 37.65% 37.65% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 67318590 17.27% 54.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 64772838 16.62% 71.54% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 47064670 12.07% 83.61% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 29521584 7.57% 91.19% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 16702188 4.28% 95.47% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 11171964 2.87% 98.34% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 4070461 1.04% 99.38% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 2408327 0.62% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 389803312 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 1532664 16.20% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.20% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 4929602 52.11% 68.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 2998000 31.69% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 441248731 67.42% 67.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 435633 0.07% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 147725739 22.57% 90.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 65037073 9.94% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 654447179 # Type of FU issued
|
|
system.cpu.iq.rate 1.677891 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 9460266 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.014455 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1708614343 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 987386046 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 633379143 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 179 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 280 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 663907354 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 91 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 7666119 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 49680139 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 29913 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 831675 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 20169135 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1622994 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 4397 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 8080712 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 32831376 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 2550941 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 769700415 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 729466 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 165564895 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 77029612 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 2297420 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 241239 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 2243400 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 831675 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 4474207 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 4147009 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 8621216 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 645315428 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 144284542 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 9131751 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1619631 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 207974195 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 141482846 # Number of branches executed
|
|
system.cpu.iew.exec_stores 63689653 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.654479 # Inst execution rate
|
|
system.cpu.iew.wb_sent 638544011 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 633379159 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 371951295 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 631497340 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.623876 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.588999 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 221053017 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 7266341 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 357986400 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.532725 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.266212 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 161840085 45.21% 45.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 93598872 26.15% 71.35% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 31669454 8.85% 80.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 16147172 4.51% 84.71% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 14656641 4.09% 88.81% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 6778711 1.89% 90.70% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 6277378 1.75% 92.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 3013551 0.84% 93.29% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 24004536 6.71% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 357986400 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
|
|
system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 172745233 # Number of memory references committed
|
|
system.cpu.commit.loads 115884756 # Number of loads committed
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
|
system.cpu.commit.branches 121548301 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 448454354 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 24004536 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 1103722571 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1571491093 # The number of ROB writes
|
|
system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 238235 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
|
|
system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.771996 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.771996 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.295343 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.295343 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 652860530 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 354600440 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.cc_regfile_reads 2339325657 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 397666160 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 231739115 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 764614178 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 866616 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 866616 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1114497 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 52 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 52 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 348819 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 348819 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30021 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3515389 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 3545410 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 958720 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 148153024 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 149111744 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 149111744 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2279489000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 23116485 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1829335495 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 13145 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1062.088688 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 125003617 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 14983 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 8343.029901 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1062.088688 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.518598 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.518598 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1838 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.897461 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 250061011 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 250061011 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 125003619 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 125003619 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 125003619 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 125003619 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 125003619 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 125003619 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 19366 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 19366 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 19366 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 19366 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 19366 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 19366 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 525397483 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 525397483 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 525397483 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 525397483 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 525397483 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 525397483 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 125022985 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 125022985 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 125022985 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 125022985 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 125022985 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 125022985 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000155 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000155 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000155 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000155 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000155 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000155 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27129.891717 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 27129.891717 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 27129.891717 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 27129.891717 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1332 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 88.800000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4325 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 4325 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 4325 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 4325 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 4325 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 4325 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15041 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 15041 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 15041 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 15041 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 15041 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 15041 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 373138014 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 373138014 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 373138014 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 373138014 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 373138014 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 373138014 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000120 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000120 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000120 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24808.058906 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24808.058906 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 115421 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 26962.800734 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1786499 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 146666 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 12.180730 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 88337540000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 22928.497316 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 342.512627 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 3691.790790 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.699722 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.010453 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.112665 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.822839 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31245 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2223 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7659 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21300 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953522 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 19134912 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 19134912 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 11728 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 807914 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 819642 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1114497 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1114497 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 247552 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 247552 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 11728 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1055466 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1067194 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 11728 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1055466 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1067194 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3252 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 43661 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 46913 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 101267 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 101267 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3252 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 144928 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 148180 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3252 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 144928 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 148180 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240599000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3363832250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 3604431250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7362459750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7362459750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 240599000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10726292000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 10966891000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 240599000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10726292000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 10966891000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 14980 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 851575 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 866555 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1114497 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1114497 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 52 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 52 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 348819 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 348819 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 14980 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1200394 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1215374 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 14980 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1200394 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1215374 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.217089 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051271 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.054137 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.173077 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.173077 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290314 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.290314 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.217089 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.120734 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.121921 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.217089 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.120734 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.121921 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73984.932349 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77044.324454 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76832.247991 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72703.444854 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72703.444854 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73984.932349 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74011.177964 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 74010.601971 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73984.932349 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74011.177964 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 74010.601971 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 97556 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 97556 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3249 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43648 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 46897 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101267 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 101267 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3249 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 144915 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 148164 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3249 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 144915 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 148164 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199534250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2816982750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3016517000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6081150250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6081150250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 199534250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8898133000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9097667250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 199534250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8898133000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9097667250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.216889 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051256 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054119 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.173077 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.173077 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290314 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290314 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.216889 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120723 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.121908 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.216889 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120723 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.121908 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61414.050477 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64538.644382 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64322.174126 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60050.660630 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60050.660630 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61414.050477 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61414.050477 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1196298 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4055.671895 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 184137490 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1200394 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 153.397543 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 4287130250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4055.671895 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.990154 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.990154 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 379628218 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 379628218 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 130278206 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 130278206 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 50877875 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 50877875 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 3872 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 3872 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488856 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488856 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 181156081 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 181156081 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 181159953 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 181159953 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1715015 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1715015 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 3361431 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 3361431 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 76 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 76 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 5076446 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 5076446 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 5076522 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 5076522 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29355008484 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 29355008484 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 73441852684 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 73441852684 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 636000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 636000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 102796861168 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 102796861168 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 102796861168 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 102796861168 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 131993221 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 131993221 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3948 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 3948 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488896 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488896 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 186232527 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 186232527 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 186236475 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 186236475 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012993 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.012993 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061974 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.061974 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.019250 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.019250 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000027 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000027 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.027259 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.027259 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.027258 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.027258 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17116.473316 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 17116.473316 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21848.389178 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 21848.389178 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15900 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15900 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20249.769458 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 20249.769458 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20249.466302 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 20249.466302 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 21467 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 55050 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 2269 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.460996 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 83.282905 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1114497 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1114497 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862982 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 862982 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3013069 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3013069 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3876051 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3876051 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3876051 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3876051 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 852033 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 852033 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348362 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 348362 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 51 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 51 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1200395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1200395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1200446 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1200446 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12334131763 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12334131763 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10183047234 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10183047234 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2581000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2581000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22517178997 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 22517178997 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22519759997 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 22519759997 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006455 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006455 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.012918 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006446 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006446 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14476.119778 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14476.119778 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29231.222791 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29231.222791 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50607.843137 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50607.843137 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18758.141276 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18758.141276 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18759.494385 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18759.494385 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|