gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
Andreas Hansson a217eba078 stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
2014-09-03 07:42:59 -04:00

1555 lines
184 KiB
Text

---------- Begin Simulation Statistics ----------
sim_seconds 5.129874 # Number of seconds simulated
sim_ticks 5129873616500 # Number of ticks simulated
final_tick 5129873616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 122712 # Simulator instruction rate (inst/s)
host_op_rate 242564 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1543734215 # Simulator tick rate (ticks/s)
host_mem_usage 750608 # Number of bytes of host memory used
host_seconds 3323.03 # Real time elapsed on the host
sim_insts 407773893 # Number of instructions simulated
sim_ops 806048632 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1049344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10817792 # Number of bytes read from this memory
system.physmem.bytes_read::total 11900032 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1049344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1049344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6600896 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
system.physmem.bytes_written::total 9590976 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 16396 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 169028 # Number of read requests responded to by this memory
system.physmem.num_reads::total 185938 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 103139 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149859 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 823 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 204556 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2108783 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2319751 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 204556 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 204556 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1286756 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1869632 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1286756 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 588403 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 823 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 204556 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2108783 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4189384 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 185938 # Number of read requests accepted
system.physmem.writeReqs 149859 # Number of write requests accepted
system.physmem.readBursts 185938 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 149859 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11881152 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue
system.physmem.bytesWritten 9589248 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 11900032 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 9590976 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 1710 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11383 # Per bank write bursts
system.physmem.perBankRdBursts::1 10659 # Per bank write bursts
system.physmem.perBankRdBursts::2 11850 # Per bank write bursts
system.physmem.perBankRdBursts::3 11657 # Per bank write bursts
system.physmem.perBankRdBursts::4 11883 # Per bank write bursts
system.physmem.perBankRdBursts::5 11508 # Per bank write bursts
system.physmem.perBankRdBursts::6 11028 # Per bank write bursts
system.physmem.perBankRdBursts::7 11462 # Per bank write bursts
system.physmem.perBankRdBursts::8 11217 # Per bank write bursts
system.physmem.perBankRdBursts::9 11477 # Per bank write bursts
system.physmem.perBankRdBursts::10 11649 # Per bank write bursts
system.physmem.perBankRdBursts::11 12129 # Per bank write bursts
system.physmem.perBankRdBursts::12 11737 # Per bank write bursts
system.physmem.perBankRdBursts::13 12518 # Per bank write bursts
system.physmem.perBankRdBursts::14 12268 # Per bank write bursts
system.physmem.perBankRdBursts::15 11218 # Per bank write bursts
system.physmem.perBankWrBursts::0 10090 # Per bank write bursts
system.physmem.perBankWrBursts::1 9375 # Per bank write bursts
system.physmem.perBankWrBursts::2 9103 # Per bank write bursts
system.physmem.perBankWrBursts::3 8918 # Per bank write bursts
system.physmem.perBankWrBursts::4 9314 # Per bank write bursts
system.physmem.perBankWrBursts::5 9243 # Per bank write bursts
system.physmem.perBankWrBursts::6 8603 # Per bank write bursts
system.physmem.perBankWrBursts::7 8925 # Per bank write bursts
system.physmem.perBankWrBursts::8 9240 # Per bank write bursts
system.physmem.perBankWrBursts::9 9268 # Per bank write bursts
system.physmem.perBankWrBursts::10 9747 # Per bank write bursts
system.physmem.perBankWrBursts::11 9397 # Per bank write bursts
system.physmem.perBankWrBursts::12 9475 # Per bank write bursts
system.physmem.perBankWrBursts::13 9702 # Per bank write bursts
system.physmem.perBankWrBursts::14 10013 # Per bank write bursts
system.physmem.perBankWrBursts::15 9419 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
system.physmem.totGap 5129873502000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 185938 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 149859 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 170868 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 11901 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 408 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 52 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2274 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 7218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 7696 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 8666 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 8996 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 9690 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 10286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 11378 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 10590 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9936 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9091 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8900 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7590 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 251 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 71875 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 298.717718 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 177.081512 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 320.465816 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 27438 38.17% 38.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17395 24.20% 62.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 7359 10.24% 72.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 4225 5.88% 78.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2947 4.10% 82.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2054 2.86% 85.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1404 1.95% 87.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1166 1.62% 89.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7887 10.97% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 71875 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7354 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 25.241501 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 560.072825 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 7353 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7354 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7354 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.374218 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.656947 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.477131 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 6319 85.93% 85.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 51 0.69% 86.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 33 0.45% 87.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 263 3.58% 90.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 273 3.71% 94.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 24 0.33% 94.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 24 0.33% 95.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 15 0.20% 95.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 39 0.53% 95.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 6 0.08% 95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 3 0.04% 95.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 1 0.01% 95.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 229 3.11% 98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.07% 99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 3 0.04% 99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 2 0.03% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 25 0.34% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 13 0.18% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 5 0.07% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 2 0.03% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 10 0.14% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7354 # Writes before turning the bus around for reads
system.physmem.totQLat 1988147750 # Total ticks spent queuing
system.physmem.totMemAccLat 5468954000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 928215000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10709.52 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29459.52 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.59 # Average write queue length when enqueuing
system.physmem.readRowHits 152685 # Number of row buffer hits during reads
system.physmem.writeRowHits 110914 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes
system.physmem.avgGap 15276710.34 # Average gap between requests
system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 4923726743250 # Time in different power states
system.physmem.memoryStateTime::REF 171297620000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 34849149750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 4545861 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 662568 # Transaction distribution
system.membus.trans_dist::ReadResp 662557 # Transaction distribution
system.membus.trans_dist::WriteReq 13776 # Transaction distribution
system.membus.trans_dist::WriteResp 13776 # Transaction distribution
system.membus.trans_dist::Writeback 103139 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2217 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1710 # Transaction distribution
system.membus.trans_dist::ReadExReq 133156 # Transaction distribution
system.membus.trans_dist::ReadExResp 133153 # Transaction distribution
system.membus.trans_dist::MessageReq 1644 # Transaction distribution
system.membus.trans_dist::MessageResp 1644 # Transaction distribution
system.membus.trans_dist::BadAddressError 11 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478059 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 22 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724235 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94797 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 94797 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1822320 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18472576 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20264541 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 23289549 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 23289549 # Total data (bytes)
system.membus.snoop_data_through_bus 30144 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 251288000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 583699000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer3.occupancy 1574361000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 3158618040 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
system.membus.respLayer4.occupancy 54966743 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 47579 # number of replacements
system.iocache.tags.tagsinuse 0.103859 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 4992945696000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103859 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006491 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.006491 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 428706 # Number of tag accesses
system.iocache.tags.data_accesses 428706 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses
system.iocache.ReadReq_misses::total 914 # number of ReadReq misses
system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses
system.iocache.demand_misses::total 914 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses
system.iocache.overall_misses::total 914 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152667446 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 152667446 # number of ReadReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 152667446 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 152667446 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 152667446 # number of overall miss cycles
system.iocache.overall_miss_latency::total 152667446 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 167032.216630 # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 167032.216630 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 167032.216630 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 46720 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 914 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 914 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 914 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 914 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 105114946 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2850047667 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2850047667 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 105114946 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 105114946 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 115005.411379 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61002.732598 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61002.732598 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.throughput 638663 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 225570 # Transaction distribution
system.iobus.trans_dist::ReadResp 225570 # Transaction distribution
system.iobus.trans_dist::WriteReq 57606 # Transaction distribution
system.iobus.trans_dist::WriteResp 57606 # Transaction distribution
system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 3276260 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 3276260 # Total data (bytes)
system.iobus.reqLayer0.occupancy 3918185 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 422017356 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 52370257 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 86877356 # Number of BP lookups
system.cpu.branchPred.condPredicted 86877356 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 902542 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 80133511 # Number of BTB lookups
system.cpu.branchPred.BTBHits 78163225 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 97.541246 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1555611 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 178528 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.numCycles 449309558 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 27651859 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 428959611 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86877356 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 79718836 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 417653044 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1892712 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 141479 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 49827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 205407 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 127451 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9182196 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 444767 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5009 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 446775840 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.894723 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.051895 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 281257253 62.95% 62.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2318085 0.52% 63.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 72134929 16.15% 79.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1613434 0.36% 79.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2149929 0.48% 80.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2328393 0.52% 80.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1530698 0.34% 81.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1882713 0.42% 81.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 81560406 18.26% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 446775840 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.193357 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.954708 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 23023114 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 264661195 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 150717323 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 7427852 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 946356 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 838299668 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 946356 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 25879231 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 223164657 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 13208529 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 154609969 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 28967098 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 834812666 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 479412 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 12346095 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 191662 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 13684658 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 997151203 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1813191058 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1114665342 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 185 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 963963482 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 33187719 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 468373 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 472487 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 39006494 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 17336272 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10188880 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1345741 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1123547 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 829275749 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1209290 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 824021244 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 242579 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 23492118 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 36175819 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 154222 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 446775840 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.844373 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.418251 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 262561849 58.77% 58.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 13882888 3.11% 61.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10086827 2.26% 64.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6921999 1.55% 65.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 74315249 16.63% 82.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4452451 1.00% 83.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72780033 16.29% 99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1201096 0.27% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 573448 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 446775840 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1974933 71.79% 71.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 151 0.01% 71.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 606 0.02% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.81% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 614459 22.33% 94.15% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 161026 5.85% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 292875 0.04% 0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 795624977 96.55% 96.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 125321 0.02% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 18429310 2.24% 98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9398312 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 824021244 # Type of FU issued
system.cpu.iq.rate 1.833972 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2751175 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.003339 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2097811864 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 853989635 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 819447653 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 217 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 826479445 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 99 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1882501 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 3343168 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14800 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 14469 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1764190 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2224524 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 72794 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 946356 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 205489198 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 9385897 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 830485039 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 188872 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 17336272 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 10188880 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 713065 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 415930 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 8070911 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14469 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 518528 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 536731 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1055259 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 822394413 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 18030482 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1492613 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 27200783 # number of memory reference insts executed
system.cpu.iew.exec_branches 83281301 # Number of branches executed
system.cpu.iew.exec_stores 9170301 # Number of stores executed
system.cpu.iew.exec_rate 1.830351 # Inst execution rate
system.cpu.iew.wb_sent 821885746 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 819447713 # cumulative count of insts written-back
system.cpu.iew.wb_producers 640810294 # num instructions producing a value
system.cpu.iew.wb_consumers 1050192124 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.823793 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.610184 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 24342460 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1055068 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 914367 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 443118746 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.819035 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.675250 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 272366005 61.47% 61.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11194221 2.53% 63.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3590232 0.81% 64.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 74521712 16.82% 81.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2434404 0.55% 82.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1603700 0.36% 82.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 952599 0.21% 82.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 71009883 16.03% 98.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5445990 1.23% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 443118746 # Number of insts commited each cycle
system.cpu.commit.committedInsts 407773893 # Number of instructions committed
system.cpu.commit.committedOps 806048632 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 22417793 # Number of memory references committed
system.cpu.commit.loads 13993103 # Number of loads committed
system.cpu.commit.membars 474875 # Number of memory barriers committed
system.cpu.commit.branches 82158924 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 734892496 # Number of committed integer instructions.
system.cpu.commit.function_calls 1155452 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 174150 0.02% 0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 783190673 97.16% 97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 144749 0.02% 97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 121267 0.02% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 13993103 1.74% 98.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 8424690 1.05% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 806048632 # Class of committed instruction
system.cpu.commit.bw_lim_events 5445990 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1267985613 # The number of ROB reads
system.cpu.rob.rob_writes 1664458820 # The number of ROB writes
system.cpu.timesIdled 297027 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 2533718 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9810435335 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 407773893 # Number of Instructions Simulated
system.cpu.committedOps 806048632 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.101860 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.101860 # CPI: Total CPI of All Threads
system.cpu.ipc 0.907557 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.907557 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1092201088 # number of integer regfile reads
system.cpu.int_regfile_writes 655889202 # number of integer regfile writes
system.cpu.fp_regfile_reads 60 # number of floating regfile reads
system.cpu.cc_regfile_reads 416095530 # number of cc regfile reads
system.cpu.cc_regfile_writes 321948927 # number of cc regfile writes
system.cpu.misc_regfile_reads 265553416 # number of misc regfile reads
system.cpu.misc_regfile_writes 402606 # number of misc regfile writes
system.cpu.toL2Bus.throughput 55008962 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 3071462 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 3070914 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1585837 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2242 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2242 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 287030 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 287030 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 11 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1996026 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130754 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30653 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 164256 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8321689 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63869504 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207903453 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 978368 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5729920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 278481245 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 278457117 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 3731904 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4072507880 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1501244795 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3142652109 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 23061226 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 112150627 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 997506 # number of replacements
system.cpu.icache.tags.tagsinuse 509.982226 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 8120756 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 998018 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 8.136883 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 147598371250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 509.982226 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996059 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.996059 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 10180257 # Number of tag accesses
system.cpu.icache.tags.data_accesses 10180257 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 8120756 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 8120756 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 8120756 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 8120756 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 8120756 # number of overall hits
system.cpu.icache.overall_hits::total 8120756 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1061436 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1061436 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1061436 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1061436 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1061436 # number of overall misses
system.cpu.icache.overall_misses::total 1061436 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14736249127 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14736249127 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14736249127 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14736249127 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14736249127 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14736249127 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9182192 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9182192 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9182192 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9182192 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9182192 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9182192 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115597 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.115597 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.115597 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.115597 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.115597 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.115597 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13883.313857 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13883.313857 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13883.313857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13883.313857 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 6673 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 22.852740 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63371 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 63371 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 63371 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 63371 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 63371 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 63371 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 998065 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 998065 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 998065 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 998065 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 998065 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 998065 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095503951 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12095503951 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095503951 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12095503951 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095503951 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12095503951 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108696 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.108696 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.108696 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12118.954127 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12118.954127 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements 14491 # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse 6.005977 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 26506 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 14506 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 1.827244 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5104029760000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.005977 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375374 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.375374 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses 99110 # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses 99110 # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26504 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 26504 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26506 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 26506 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26506 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 26506 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15366 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 15366 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15366 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 15366 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15366 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 15366 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 173869741 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 173869741 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 173869741 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 173869741 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 173869741 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 173869741 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41870 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 41870 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41872 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 41872 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41872 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 41872 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.366993 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.366993 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.366976 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.366976 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.366976 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.366976 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11315.224587 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11315.224587 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11315.224587 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11315.224587 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks 2963 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 2963 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15366 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15366 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15366 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 15366 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15366 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 15366 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143113289 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143113289 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143113289 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143113289 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143113289 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143113289 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.366993 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.366993 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.366976 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.366976 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9313.633281 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements 73624 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 15.198399 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 115934 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 73640 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.574335 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 3233327929250 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.198399 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.949900 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.949900 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses 456046 # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses 456046 # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 115934 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 115934 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 115934 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 115934 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 115934 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 115934 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74726 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 74726 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74726 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 74726 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74726 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 74726 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 911611211 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 911611211 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 911611211 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 911611211 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 911611211 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 911611211 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190660 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 190660 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190660 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 190660 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190660 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 190660 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391933 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391933 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391933 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391933 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391933 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391933 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12199.384565 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12199.384565 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12199.384565 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12199.384565 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks 22207 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 22207 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74726 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74726 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74726 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 74726 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74726 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 74726 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 762035957 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 762035957 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 762035957 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 762035957 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 762035957 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 762035957 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391933 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391933 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391933 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10197.735152 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 1659582 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.996805 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 19130892 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1660094 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.523981 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.996805 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 88336593 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 88336593 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 10981431 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10981431 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8081664 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8081664 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 65027 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 65027 # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data 19063095 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 19063095 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 19128122 # number of overall hits
system.cpu.dcache.overall_hits::total 19128122 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1801191 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1801191 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 333463 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 333463 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 406345 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 406345 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 2134654 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2134654 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2540999 # number of overall misses
system.cpu.dcache.overall_misses::total 2540999 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 26558757753 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 26558757753 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12819840878 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12819840878 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 39378598631 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 39378598631 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 39378598631 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 39378598631 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 12782622 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 12782622 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8415127 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8415127 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 471372 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 471372 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21197749 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21197749 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21669121 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21669121 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140909 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.140909 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039627 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.039627 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862047 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.862047 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.100702 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.100702 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.117264 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117264 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.109071 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.109071 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38444.567697 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38444.567697 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18447.298078 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18447.298078 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15497.290094 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15497.290094 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 378253 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 40145 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.422170 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1560667 # number of writebacks
system.cpu.dcache.writebacks::total 1560667 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 830878 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 830878 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44317 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 44317 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 875195 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 875195 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 875195 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 875195 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970313 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 970313 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289146 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 289146 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402890 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 402890 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1259459 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1259459 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1662349 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1662349 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12260897766 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12260897766 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11156657127 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11156657127 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5584385500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5584385500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23417554893 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23417554893 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29001940393 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29001940393 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364665000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364665000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539423000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539423000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99904088000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 99904088000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075909 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075909 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034360 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034360 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854718 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854718 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059415 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.059415 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076715 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076715 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.023392 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.023392 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38584.857224 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38584.857224 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13860.819330 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13860.819330 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18593.344359 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18593.344359 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17446.360778 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17446.360778 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 112856 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64816.166677 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3836348 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 176998 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 21.674527 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50391.724726 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.855148 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135532 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3265.471036 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11143.980235 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.768917 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000227 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049827 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.170044 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.989016 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64142 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 609 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3329 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5865 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54284 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978729 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 35070365 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 35070365 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67257 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12319 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 981564 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1336552 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2397692 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1585837 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1585837 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 306 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 306 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 153585 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 153585 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 67257 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 12319 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 981564 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1490137 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2551277 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 67257 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 12319 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 981564 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1490137 # number of overall hits
system.cpu.l2cache.overall_hits::total 2551277 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 16397 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 35888 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 52356 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1429 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1429 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133434 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133434 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 16397 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 169322 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 16397 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169322 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5156250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 377750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1256760500 # number of ReadReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16426795 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 16426795 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9290345968 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9290345968 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5156250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 377750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1256760500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 13389695967 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5156250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 377750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1256760500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12127401467 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13389695967 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67323 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 997961 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1372440 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2450048 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1585837 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1585837 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1735 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1735 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 287019 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 287019 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67323 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 12324 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 997961 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1659459 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2737067 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67323 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 12324 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 997961 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1659459 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2737067 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000980 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000406 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016431 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026149 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021369 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823631 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823631 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464896 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.464896 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000980 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000406 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016431 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102034 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.067879 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000980 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000406 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016431 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102034 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.067879 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78125 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75550 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76645.758370 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79053.039986 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 78297.616300 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11495.307908 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11495.307908 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69625.027864 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69625.027864 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78125 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75550 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76645.758370 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71623.306286 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72068.980930 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78125 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75550 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76645.758370 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71623.306286 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72068.980930 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 103139 # number of writebacks
system.cpu.l2cache.writebacks::total 103139 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16396 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35886 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 52353 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1429 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1429 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133434 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133434 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16396 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 169320 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 185787 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16396 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169320 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 185787 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4346250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 315250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1051024500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2391844499 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3447530499 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14329428 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14329428 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7615118032 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7615118032 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4346250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 315250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1051024500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006962531 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11062648531 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4346250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 315250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1051024500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006962531 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11062648531 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251423000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251423000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373128500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373128500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624551500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624551500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000980 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000406 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016429 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026148 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021368 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823631 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823631 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464896 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464896 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000980 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000406 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016429 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102033 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.067878 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000980 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000406 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016429 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102033 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.067878 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64102.494511 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66651.187065 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65851.632170 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.591323 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.591323 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57070.297166 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57070.297166 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64102.494511 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.889033 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59544.793398 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64102.494511 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.889033 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59544.793398 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------