a217eba078
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
1456 lines
168 KiB
Plaintext
1456 lines
168 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.860009 # Number of seconds simulated
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sim_ticks 1860008936000 # Number of ticks simulated
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final_tick 1860008936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 106543 # Simulator instruction rate (inst/s)
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host_op_rate 106543 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3740252336 # Simulator tick rate (ticks/s)
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host_mem_usage 320492 # Number of bytes of host memory used
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host_seconds 497.30 # Real time elapsed on the host
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sim_insts 52983264 # Number of instructions simulated
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sim_ops 52983264 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 968512 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24900352 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25869824 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 968512 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 968512 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4866048 # Number of bytes written to this memory
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system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7525376 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 15133 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 389068 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 404216 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 76032 # Number of write requests responded to by this memory
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system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 117584 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 520703 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 13387222 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13908441 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 520703 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 520703 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2616142 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::tsunami.ide 1429739 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4045882 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2616142 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 520703 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 13387222 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1430255 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17954322 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 404216 # Number of read requests accepted
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system.physmem.writeReqs 117584 # Number of write requests accepted
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system.physmem.readBursts 404216 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 117584 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25858752 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25869824 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7525376 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 213 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25622 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25451 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25608 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25528 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25399 # Per bank write bursts
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system.physmem.perBankRdBursts::5 24757 # Per bank write bursts
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system.physmem.perBankRdBursts::6 24940 # Per bank write bursts
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system.physmem.perBankRdBursts::7 25074 # Per bank write bursts
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system.physmem.perBankRdBursts::8 24966 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25053 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25586 # Per bank write bursts
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system.physmem.perBankRdBursts::11 24884 # Per bank write bursts
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system.physmem.perBankRdBursts::12 24485 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25285 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25789 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25616 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7925 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7509 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7974 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7525 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7335 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6682 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6769 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6701 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7135 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6719 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7431 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6970 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7113 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7882 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8065 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7817 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
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system.physmem.totGap 1860003602000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 404216 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 117584 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 37801 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 42911 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 8183 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1589 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2253 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3103 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4140 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5361 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 6916 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 7275 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 8550 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 9031 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 8802 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 9048 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7865 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7965 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6074 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5926 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5563 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 182 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 134 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 119 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 61090 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 546.434703 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 336.353089 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 417.871718 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 13232 21.66% 21.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 10443 17.09% 38.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 4742 7.76% 46.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2710 4.44% 50.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2446 4.00% 54.96% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1597 2.61% 57.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1401 2.29% 59.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1610 2.64% 62.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 22909 37.50% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 61090 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5256 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 76.868151 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 2912.510758 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-8191 5253 99.94% 99.94% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5256 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5256 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 22.365297 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 19.103318 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 20.103778 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-19 4494 85.50% 85.50% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20-23 124 2.36% 87.86% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24-27 9 0.17% 88.03% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::28-31 232 4.41% 92.45% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32-35 40 0.76% 93.21% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::36-39 6 0.11% 93.32% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::40-43 12 0.23% 93.55% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::44-47 3 0.06% 93.61% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::48-51 27 0.51% 94.12% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::52-55 3 0.06% 94.18% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::56-59 1 0.02% 94.20% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::60-63 1 0.02% 94.22% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::64-67 15 0.29% 94.50% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::68-71 5 0.10% 94.60% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::72-75 3 0.06% 94.65% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::80-83 31 0.59% 95.24% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::84-87 8 0.15% 95.40% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::88-91 4 0.08% 95.47% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::92-95 5 0.10% 95.57% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::96-99 188 3.58% 99.14% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::108-111 2 0.04% 99.18% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::112-115 5 0.10% 99.28% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::124-127 3 0.06% 99.33% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::128-131 11 0.21% 99.54% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::132-135 3 0.06% 99.60% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::136-139 1 0.02% 99.62% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::140-143 7 0.13% 99.75% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::144-147 5 0.10% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 2 0.04% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 2 0.04% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5256 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 3626109250 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 11201915500 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2020215000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 8974.56 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 27724.56 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 4.05 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.14 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 364992 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 95512 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 81.23 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3564591.03 # Average gap between requests
|
|
system.physmem.pageHitRate 88.28 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 1761923491250 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 62109580000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 35970256750 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.membus.throughput 17983494 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 296097 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 296008 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9598 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9598 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 76032 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 207 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 213 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 115296 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 115296 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 89 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884860 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 918094 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1001386 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30734912 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30779060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 33439348 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 33439348 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 29284000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1484965250 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 112000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 3755505039 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.268186 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1709354954000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.268186 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.079262 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.079262 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 376037 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 376037 # Number of data accesses
|
|
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
|
|
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::tsunami.ide 64 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 64 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
|
|
system.iocache.overall_misses::total 173 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41616 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 41616 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.001538 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 0.001538 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 41552 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2528134047 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2528134047 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.998462 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.998462 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60842.656118 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60842.656118 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu.branchPred.lookups 17833670 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 15506350 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 381114 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 12104225 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 5926115 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 48.959062 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 921355 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 21398 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 10317598 # DTB read hits
|
|
system.cpu.dtb.read_misses 42841 # DTB read misses
|
|
system.cpu.dtb.read_acv 498 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 968680 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6661505 # DTB write hits
|
|
system.cpu.dtb.write_misses 9470 # DTB write misses
|
|
system.cpu.dtb.write_acv 409 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 342844 # DTB write accesses
|
|
system.cpu.dtb.data_hits 16979103 # DTB hits
|
|
system.cpu.dtb.data_misses 52311 # DTB misses
|
|
system.cpu.dtb.data_acv 907 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1311524 # DTB accesses
|
|
system.cpu.itb.fetch_hits 1772041 # ITB hits
|
|
system.cpu.itb.fetch_misses 34420 # ITB misses
|
|
system.cpu.itb.fetch_acv 658 # ITB acv
|
|
system.cpu.itb.fetch_accesses 1806461 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 118354133 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 29610053 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 78304025 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 17833670 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 6847470 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 80574615 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1256858 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 1099 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 26263 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 1650622 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 440507 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 9057340 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 272482 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 112931823 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.693374 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.013486 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 98319716 87.06% 87.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 938849 0.83% 87.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1975725 1.75% 89.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 910849 0.81% 90.45% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2798510 2.48% 92.93% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 647409 0.57% 93.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 732146 0.65% 94.15% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1011734 0.90% 95.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 5596885 4.96% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 112931823 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.150681 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.661608 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 24101711 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 76820135 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 9519710 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 1904377 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 585889 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 591731 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 42945 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 68430953 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 130896 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 585889 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 25024532 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 47243324 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 20763433 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 10413926 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 8900717 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 65988448 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 204336 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2037147 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 141186 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 4759131 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 44017538 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 79991288 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 79809724 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 169111 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 38182266 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 5835264 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1692739 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 242112 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13540611 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 10451547 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 6960595 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1482211 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1061862 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 58727790 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2141622 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 57666213 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 56106 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 7541795 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 3548748 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1480432 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 112931823 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.510629 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.253101 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 89418441 79.18% 79.18% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 10028401 8.88% 88.06% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 4312192 3.82% 91.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 2973812 2.63% 94.51% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 3078524 2.73% 97.24% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 1589541 1.41% 98.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1010242 0.89% 99.54% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 396621 0.35% 99.89% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 124049 0.11% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 112931823 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 207021 18.24% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.24% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 552834 48.70% 66.94% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 375297 33.06% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 39135351 67.87% 67.88% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 61883 0.11% 67.99% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 38374 0.07% 68.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 10730394 18.61% 86.67% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 6740242 11.69% 98.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 949047 1.65% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 57666213 # Type of FU issued
|
|
system.cpu.iq.rate 0.487234 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 1135152 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.019685 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 228740415 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 68094123 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 55977641 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 715091 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 336647 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 329707 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 58410087 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 383992 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 639401 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1358213 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 20004 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 581979 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 18257 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 542602 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 585889 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 44309531 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 608680 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 64580146 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 145680 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 10451547 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 6960595 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1891521 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 42330 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 362520 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 20004 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 191994 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 411566 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 603560 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 57078103 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 10388088 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 588109 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 3710734 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 17074164 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 8987700 # Number of branches executed
|
|
system.cpu.iew.exec_stores 6686076 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.482265 # Inst execution rate
|
|
system.cpu.iew.wb_sent 56446206 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 56307348 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 28961590 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 40346871 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.475753 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.717815 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 8290413 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 661190 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 549582 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 111493844 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.503831 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.456125 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 91848046 82.38% 82.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 7822356 7.02% 89.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4123652 3.70% 93.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2157766 1.94% 95.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1851713 1.66% 96.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 614180 0.55% 97.24% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 473259 0.42% 97.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 509141 0.46% 98.12% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 2093731 1.88% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 111493844 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 56174099 # Number of instructions committed
|
|
system.cpu.commit.committedOps 56174099 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 15471950 # Number of memory references committed
|
|
system.cpu.commit.loads 9093334 # Number of loads committed
|
|
system.cpu.commit.membars 226345 # Number of memory barriers committed
|
|
system.cpu.commit.branches 8441019 # Number of branches committed
|
|
system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 52023449 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 740634 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 3198108 5.69% 5.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 36220301 64.48% 70.17% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 60671 0.11% 70.28% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 9319679 16.59% 86.94% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 6384570 11.37% 98.31% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 949047 1.69% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 56174099 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 2093731 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 173614429 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 130369620 # The number of ROB writes
|
|
system.cpu.timesIdled 576556 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 5422310 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 3601657297 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 52983264 # Number of Instructions Simulated
|
|
system.cpu.committedOps 52983264 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 2.233802 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 2.233802 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.447667 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.447667 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 74755796 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 40630218 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 167440 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 167913 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2030226 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 939431 # number of misc regfile writes
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.iobus.throughput 1454701 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51086 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51150 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateReq 64 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 2705756 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 374510641 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.throughput 114654995 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2149538 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2149432 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 845214 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 94 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 122 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 302210 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 302210 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074480 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3693292 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 5767772 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66377344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144210036 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 210587380 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 210577396 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 2681920 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2503268997 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1560084006 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2193039668 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 1036559 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 509.401978 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 7968978 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1037067 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 7.684150 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 26427286250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 509.401978 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 10094673 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 10094673 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 7968979 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 7968979 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 7968979 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 7968979 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 7968979 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 7968979 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1088360 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1088360 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1088360 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1088360 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1088360 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1088360 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15140469933 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 15140469933 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 15140469933 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 15140469933 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 15140469933 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 15140469933 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 9057339 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 9057339 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 9057339 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 9057339 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 9057339 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 9057339 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120163 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.120163 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.120163 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.120163 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.120163 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.120163 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13911.270106 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13911.270106 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13911.270106 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13911.270106 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 4471 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 200 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 22.355000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51026 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 51026 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 51026 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 51026 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 51026 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 51026 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037334 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1037334 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1037334 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1037334 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1037334 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1037334 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12446794989 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 12446794989 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12446794989 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 12446794989 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12446794989 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 12446794989 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114530 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.114530 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.114530 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.830646 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.830646 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 338424 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65337.415563 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2581710 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 403590 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 6.396863 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 5538438750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 53805.196085 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5357.724352 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 6174.495125 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.821002 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081752 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.094215 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.996970 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3497 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3323 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55433 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 27024459 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 27024459 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1022012 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 831240 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1853252 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 845214 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 845214 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 186775 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 186775 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1022012 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1018015 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2040027 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1022012 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1018015 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2040027 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 15134 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 273861 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 288995 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 68 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 68 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 115435 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 115435 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 15134 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 389296 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 404430 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 15134 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 389296 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 404430 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1158853750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17990415250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 19149269000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 271990 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 271990 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9647831862 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 9647831862 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1158853750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 27638247112 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 28797100862 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1158853750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 27638247112 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 28797100862 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1037146 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1105101 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2142247 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 845214 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 845214 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 94 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 94 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 302210 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 302210 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1037146 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1407311 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2444457 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1037146 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1407311 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2444457 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014592 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.247815 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.134903 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.723404 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.723404 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.381969 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.381969 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014592 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.276624 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.165448 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014592 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.276624 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.165448 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76572.865733 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65691.775207 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66261.592761 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3999.852941 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3999.852941 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 7833 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 7833 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83578.047057 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83578.047057 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76572.865733 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70995.456188 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 71204.166016 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76572.865733 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70995.456188 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 71204.166016 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 76032 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 76032 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15133 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273861 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 288994 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 68 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 68 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115435 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 115435 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15133 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 389296 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 404429 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15133 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 389296 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 404429 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967955000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14578847250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15546802250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 698067 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 698067 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 60006 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 60006 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8240977138 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8240977138 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967955000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22819824388 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 23787779388 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967955000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22819824388 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 23787779388 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333197000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333197000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882784000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882784000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3215981000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3215981000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.247815 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.134902 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.723404 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.723404 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.381969 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.381969 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276624 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.165447 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276624 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.165447 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63963.193022 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53234.477527 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53796.280373 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10265.691176 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10265.691176 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71390.627955 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71390.627955 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63963.193022 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58618.183562 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58818.184126 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63963.193022 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58618.183562 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58818.184126 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1406709 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.994656 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 11889160 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1407221 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 8.448680 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994656 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 64006618 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 64006618 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7294645 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7294645 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4192085 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4192085 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 186406 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 186406 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 215722 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 215722 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 11486730 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 11486730 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 11486730 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 11486730 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1781450 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1781450 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1956078 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1956078 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 23435 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 23435 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3737528 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3737528 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3737528 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3737528 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39460898751 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 39460898751 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 77926098572 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 77926098572 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 366682499 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 366682499 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 440006 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 440006 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 117386997323 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 117386997323 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 117386997323 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 117386997323 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9076095 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9076095 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6148163 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6148163 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209841 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 209841 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215750 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 215750 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15224258 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15224258 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15224258 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15224258 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196279 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.196279 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318156 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.318156 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111680 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111680 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.245498 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.245498 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.245498 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.245498 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22150.999888 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 22150.999888 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39837.930068 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 39837.930068 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15646.788948 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15646.788948 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15714.500000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15714.500000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 31407.656966 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 31407.656966 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 3974317 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 2076 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 180350 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 21 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.036690 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 98.857143 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 845214 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 845214 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683673 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 683673 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664672 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1664672 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5215 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5215 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2348345 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2348345 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2348345 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2348345 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1097777 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1097777 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291406 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 291406 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18220 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 18220 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1389183 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1389183 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1389183 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1389183 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27531600277 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27531600277 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11750999106 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11750999106 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 207629251 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 207629251 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 383994 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 383994 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39282599383 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 39282599383 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39282599383 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 39282599383 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423287000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423287000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997974498 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997974498 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421261498 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421261498 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120953 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120953 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047397 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047397 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086828 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086828 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25079.410734 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25079.410734 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40325.178981 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40325.178981 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11395.677881 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.677881 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13714.071429 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13714.071429 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211008 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105564 57.93% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182238 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1818262027500 97.76% 97.76% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 61927000 0.00% 97.76% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 526143500 0.03% 97.79% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 41157993000 2.21% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1860008091000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694328 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.815434 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175121 91.22% 93.43% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 191967 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1910
|
|
system.cpu.kern.mode_good::user 1740
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch_good::kernel 0.326496 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 29080060000 1.56% 1.56% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 2655672500 0.14% 1.71% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1828272350500 98.29% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
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