a2113fd3dc
src/cpu/o3/alpha/cpu_impl.hh: Handle the PhysicalPort and VirtualPort in the ThreadState. src/cpu/o3/cpu.cc: Initialize the thread context. src/cpu/o3/thread_context.hh: Add new function to initialize thread context. src/cpu/o3/thread_context_impl.hh: Use code now put into function. src/cpu/simple_thread.cc: Move code to ThreadState and use the new helper function. src/cpu/simple_thread.hh: Remove init() in this derived class; use init() from ThreadState base class. src/cpu/thread_state.cc: Move setting up of Physical and Virtual ports here. Change getMemFuncPort() to connectToMemFunc(), which connects a port to a functional port of the memory object below the CPU. src/cpu/thread_state.hh: Update functions. --HG-- extra : convert_revision : ff254715ef0b259dc80d08f13543b63e4024ca8d
340 lines
9.6 KiB
C++
340 lines
9.6 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include "config/use_checker.hh"
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#include "arch/alpha/faults.hh"
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#include "arch/alpha/isa_traits.hh"
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#include "base/cprintf.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/checker/thread_context.hh"
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#include "sim/sim_events.hh"
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#include "sim/stats.hh"
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#include "cpu/o3/alpha/cpu.hh"
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#include "cpu/o3/alpha/params.hh"
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#include "cpu/o3/alpha/thread_context.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/thread_state.hh"
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#if FULL_SYSTEM
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#include "arch/alpha/osfpal.hh"
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#include "arch/isa_traits.hh"
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#include "arch/kernel_stats.hh"
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#include "cpu/quiesce_event.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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#endif
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template <class Impl>
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AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
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#if FULL_SYSTEM
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: FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
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#else
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: FullO3CPU<Impl>(params)
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#endif
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{
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DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n");
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// Setup any thread state.
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this->thread.resize(this->numThreads);
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for (int i = 0; i < this->numThreads; ++i) {
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#if FULL_SYSTEM
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// SMT is not supported in FS mode yet.
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assert(this->numThreads == 1);
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this->thread[i] = new Thread(this, 0);
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this->thread[i]->setStatus(ThreadContext::Suspended);
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#else
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if (i < params->workload.size()) {
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DPRINTF(O3CPU, "Workload[%i] process is %#x",
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i, this->thread[i]);
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this->thread[i] = new Thread(this, i, params->workload[i], i);
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this->thread[i]->setStatus(ThreadContext::Suspended);
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//usedTids[i] = true;
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//threadMap[i] = i;
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} else {
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//Allocate Empty thread so M5 can use later
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//when scheduling threads to CPU
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Process* dummy_proc = NULL;
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this->thread[i] = new Thread(this, i, dummy_proc, i);
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//usedTids[i] = false;
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}
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#endif // !FULL_SYSTEM
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ThreadContext *tc;
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// Setup the TC that will serve as the interface to the threads/CPU.
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AlphaTC<Impl> *alpha_tc =
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new AlphaTC<Impl>;
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tc = alpha_tc;
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// If we're using a checker, then the TC should be the
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// CheckerThreadContext.
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#if USE_CHECKER
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if (params->checker) {
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tc = new CheckerThreadContext<AlphaTC<Impl> >(
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alpha_tc, this->checker);
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}
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#endif
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alpha_tc->cpu = this;
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alpha_tc->thread = this->thread[i];
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#if FULL_SYSTEM
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// Setup quiesce event.
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this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc);
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#endif
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// Give the thread the TC.
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this->thread[i]->tc = tc;
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// Add the TC to the CPU's list of TC's.
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this->threadContexts.push_back(tc);
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}
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for (int i=0; i < this->numThreads; i++) {
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this->thread[i]->setFuncExeInst(0);
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}
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// Sets CPU pointers. These must be set at this level because the CPU
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// pointers are defined to be the highest level of CPU class.
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this->fetch.setCPU(this);
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this->decode.setCPU(this);
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this->rename.setCPU(this);
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this->iew.setCPU(this);
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this->commit.setCPU(this);
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this->rob.setCPU(this);
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this->regFile.setCPU(this);
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lockAddr = 0;
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lockFlag = false;
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}
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template <class Impl>
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void
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AlphaO3CPU<Impl>::regStats()
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{
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// Register stats for everything that has stats.
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this->fullCPURegStats();
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this->fetch.regStats();
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this->decode.regStats();
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this->rename.regStats();
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this->iew.regStats();
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this->commit.regStats();
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}
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template <class Impl>
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TheISA::MiscReg
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AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
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{
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return this->regFile.readMiscReg(misc_reg, tid);
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}
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template <class Impl>
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TheISA::MiscReg
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AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
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{
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return this->regFile.readMiscRegWithEffect(misc_reg, tid);
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}
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template <class Impl>
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void
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AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
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{
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this->regFile.setMiscReg(misc_reg, val, tid);
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}
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template <class Impl>
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void
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AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
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unsigned tid)
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{
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this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
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}
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template <class Impl>
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void
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AlphaO3CPU<Impl>::squashFromTC(unsigned tid)
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{
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this->thread[tid]->inSyscall = true;
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this->commit.generateTCEvent(tid);
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}
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#if FULL_SYSTEM
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template <class Impl>
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void
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AlphaO3CPU<Impl>::post_interrupt(int int_num, int index)
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{
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BaseCPU::post_interrupt(int_num, index);
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if (this->thread[0]->status() == ThreadContext::Suspended) {
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DPRINTF(IPI,"Suspended Processor awoke\n");
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this->threadContexts[0]->activate();
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}
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}
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template <class Impl>
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Fault
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AlphaO3CPU<Impl>::hwrei(unsigned tid)
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{
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// Need to clear the lock flag upon returning from an interrupt.
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this->setMiscReg(AlphaISA::MISCREG_LOCKFLAG, false, tid);
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this->thread[tid]->kernelStats->hwrei();
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this->checkInterrupts = true;
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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}
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template <class Impl>
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bool
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AlphaO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
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{
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if (this->thread[tid]->kernelStats)
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this->thread[tid]->kernelStats->callpal(palFunc,
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this->threadContexts[tid]);
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switch (palFunc) {
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case PAL::halt:
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halt();
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if (--System::numSystemsRunning == 0)
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exitSimLoop("all cpus halted");
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break;
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case PAL::bpt:
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case PAL::bugchk:
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if (this->system->breakpoint())
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return false;
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break;
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}
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return true;
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}
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template <class Impl>
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Fault
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AlphaO3CPU<Impl>::getInterrupts()
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{
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// Check if there are any outstanding interrupts
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return this->interrupts.getInterrupt(this->threadContexts[0]);
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}
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template <class Impl>
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void
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AlphaO3CPU<Impl>::processInterrupts(Fault interrupt)
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{
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// Check for interrupts here. For now can copy the code that
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// exists within isa_fullsys_traits.hh. Also assume that thread 0
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// is the one that handles the interrupts.
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// @todo: Possibly consolidate the interrupt checking code.
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// @todo: Allow other threads to handle interrupts.
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assert(interrupt != NoFault);
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this->interrupts.updateIntrInfo(this->threadContexts[0]);
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DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
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this->checkInterrupts = false;
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this->trap(interrupt, 0);
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}
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#endif // FULL_SYSTEM
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template <class Impl>
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void
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AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid)
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{
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// Pass the thread's TC into the invoke method.
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fault->invoke(this->threadContexts[tid]);
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}
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#if !FULL_SYSTEM
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template <class Impl>
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void
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AlphaO3CPU<Impl>::syscall(int64_t callnum, int tid)
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{
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DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
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DPRINTF(Activity,"Activity: syscall() called.\n");
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// Temporarily increase this by one to account for the syscall
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// instruction.
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++(this->thread[tid]->funcExeInst);
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// Execute the actual syscall.
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this->thread[tid]->syscall(callnum);
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// Decrease funcExeInst by one as the normal commit will handle
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// incrementing it.
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--(this->thread[tid]->funcExeInst);
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}
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template <class Impl>
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TheISA::IntReg
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AlphaO3CPU<Impl>::getSyscallArg(int i, int tid)
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{
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return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid);
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}
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template <class Impl>
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void
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AlphaO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
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{
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this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
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}
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template <class Impl>
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void
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AlphaO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
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{
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// check for error condition. Alpha syscall convention is to
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// indicate success/failure in reg a3 (r19) and put the
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// return value itself in the standard return value reg (v0).
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if (return_value.successful()) {
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// no error
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this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid);
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this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid);
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} else {
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// got an error, return details
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this->setArchIntReg(TheISA::SyscallSuccessReg, (IntReg) -1, tid);
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this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid);
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}
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}
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#endif
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