0379a27896
into zower.eecs.umich.edu:/z/alschult/DiskModel/linux --HG-- extra : convert_revision : b23a1d1a79ac5c593150d269d0523c474cf6a4a0
701 lines
21 KiB
C++
701 lines
21 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cstddef>
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#include <cstdlib>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/intr_control.hh"
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#include "dev/dma.hh"
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#include "dev/pcireg.h"
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#include "dev/pciconfigall.hh"
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#include "dev/ide_disk.hh"
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#include "dev/ide_ctrl.hh"
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#include "dev/tsunami_cchip.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/bus/dma_interface.hh"
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#include "dev/tsunami.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "mem/functional_mem/physical_memory.hh"
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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using namespace std;
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////
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// Initialization and destruction
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////
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IdeController::IdeController(const string &name, IntrControl *ic,
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const vector<IdeDisk *> &new_disks,
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MemoryController *mmu, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t, uint32_t bus_num,
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uint32_t dev_num, uint32_t func_num,
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Bus *host_bus, HierParams *hier)
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: PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
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{
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// put back pointer into Tsunami
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tsunami->disk_controller = this;
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// initialize the PIO interface addresses
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pri_cmd_addr = 0;
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pri_cmd_size = BARSize[0];
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pri_ctrl_addr = 0;
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pri_ctrl_size = BARSize[1];
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sec_cmd_addr = 0;
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sec_cmd_size = BARSize[2];
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sec_ctrl_addr = 0;
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sec_ctrl_size = BARSize[3];
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// initialize the bus master interface (BMI) address to be configured
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// via PCI
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bmi_addr = 0;
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bmi_size = BARSize[4];
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// zero out all of the registers
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memset(bmi_regs, 0, sizeof(bmi_regs));
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memset(pci_regs, 0, sizeof(pci_regs));
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// setup initial values
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*(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels
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*(uint8_t *)&bmi_regs[BMIS0] = 0x60;
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*(uint8_t *)&bmi_regs[BMIS1] = 0x60;
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// reset all internal variables
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io_enabled = false;
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bm_enabled = false;
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memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
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// create the PIO and DMA interfaces
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if (host_bus) {
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pioInterface = newPioInterface(name, hier, host_bus, this,
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&IdeController::cacheAccess);
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dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
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host_bus, 1);
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}
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// setup the disks attached to controller
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memset(disks, 0, sizeof(IdeDisk *) * 4);
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if (new_disks.size() > 3)
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panic("IDE controllers support a maximum of 4 devices attached!\n");
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for (int i = 0; i < new_disks.size(); i++) {
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disks[i] = new_disks[i];
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disks[i]->setController(this, dmaInterface);
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}
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}
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IdeController::~IdeController()
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{
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for (int i = 0; i < 4; i++)
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if (disks[i])
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delete disks[i];
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}
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////
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// Utility functions
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///
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void
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IdeController::parseAddr(const Addr &addr, Addr &offset, bool &primary,
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RegType_t &type)
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{
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offset = addr;
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if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
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offset -= pri_cmd_addr;
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type = COMMAND_BLOCK;
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primary = true;
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} else if (addr >= pri_ctrl_addr &&
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addr < (pri_ctrl_addr + pri_ctrl_size)) {
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offset -= pri_ctrl_addr;
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type = CONTROL_BLOCK;
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primary = true;
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} else if (addr >= sec_cmd_addr &&
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addr < (sec_cmd_addr + sec_cmd_size)) {
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offset -= sec_cmd_addr;
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type = COMMAND_BLOCK;
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primary = false;
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} else if (addr >= sec_ctrl_addr &&
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addr < (sec_ctrl_addr + sec_ctrl_size)) {
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offset -= sec_ctrl_addr;
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type = CONTROL_BLOCK;
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primary = false;
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} else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
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offset -= bmi_addr;
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type = BMI_BLOCK;
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primary = (offset < BMIC1) ? true : false;
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} else {
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panic("IDE controller access to invalid address: %#x\n", addr);
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}
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}
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int
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IdeController::getDisk(bool primary)
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{
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int disk = 0;
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uint8_t *devBit = &dev[0];
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if (!primary) {
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disk += 2;
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devBit = &dev[1];
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}
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disk += *devBit;
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assert(*devBit == 0 || *devBit == 1);
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return disk;
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}
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int
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IdeController::getDisk(IdeDisk *diskPtr)
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{
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for (int i = 0; i < 4; i++) {
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if ((long)diskPtr == (long)disks[i])
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return i;
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}
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return -1;
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}
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////
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// Command completion
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////
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void
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IdeController::setDmaComplete(IdeDisk *disk)
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{
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int diskNum = getDisk(disk);
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if (diskNum < 0)
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panic("Unable to find disk based on pointer %#x\n", disk);
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if (diskNum < 2) {
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// clear the start/stop bit in the command register
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bmi_regs[BMIC0] &= ~SSBM;
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// clear the bus master active bit in the status register
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bmi_regs[BMIS0] &= ~BMIDEA;
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// set the interrupt bit
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bmi_regs[BMIS0] |= IDEINTS;
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} else {
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// clear the start/stop bit in the command register
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bmi_regs[BMIC1] &= ~SSBM;
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// clear the bus master active bit in the status register
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bmi_regs[BMIS1] &= ~BMIDEA;
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// set the interrupt bit
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bmi_regs[BMIS1] |= IDEINTS;
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}
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}
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////
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// Interrupt handling
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////
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void
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IdeController::intrPost()
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{
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tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
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}
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void
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IdeController::intrClear()
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{
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tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
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}
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////
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// Bus timing and bus access functions
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////
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Tick
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IdeController::cacheAccess(MemReqPtr &req)
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{
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// @todo Add more accurate timing to cache access
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return curTick + 1000;
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}
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////
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// Read and write handling
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////
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void
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IdeController::ReadConfig(int offset, int size, uint8_t *data)
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{
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Addr origOffset = offset;
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if (offset < PCI_DEVICE_SPECIFIC) {
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PciDev::ReadConfig(offset, size, data);
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} else {
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if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
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offset -= PCI_IDE_TIMING;
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offset += IDETIM;
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if ((offset + size) > (IDETIM + 4))
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panic("PCI read of IDETIM with invalid size\n");
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} else if (offset == PCI_SLAVE_TIMING) {
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offset -= PCI_SLAVE_TIMING;
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offset += SIDETIM;
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if ((offset + size) > (SIDETIM + 1))
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panic("PCI read of SIDETIM with invalid size\n");
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} else if (offset == PCI_UDMA33_CTRL) {
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offset -= PCI_UDMA33_CTRL;
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offset += UDMACTL;
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if ((offset + size) > (UDMACTL + 1))
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panic("PCI read of UDMACTL with invalid size\n");
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} else if (offset >= PCI_UDMA33_TIMING &&
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offset < (PCI_UDMA33_TIMING + 2)) {
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offset -= PCI_UDMA33_TIMING;
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offset += UDMATIM;
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if ((offset + size) > (UDMATIM + 2))
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panic("PCI read of UDMATIM with invalid size\n");
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} else {
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panic("PCI read of unimplemented register: %x\n", offset);
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}
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memcpy((void *)data, (void *)&pci_regs[offset], size);
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}
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DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
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origOffset, offset, size, *(uint32_t *)data);
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}
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void
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IdeController::WriteConfig(int offset, int size, uint32_t data)
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{
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DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n",
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offset, size, data);
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// do standard write stuff if in standard PCI space
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if (offset < PCI_DEVICE_SPECIFIC) {
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PciDev::WriteConfig(offset, size, data);
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} else {
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if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
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offset -= PCI_IDE_TIMING;
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offset += IDETIM;
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if ((offset + size) > (IDETIM + 4))
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panic("PCI write to IDETIM with invalid size\n");
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} else if (offset == PCI_SLAVE_TIMING) {
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offset -= PCI_SLAVE_TIMING;
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offset += SIDETIM;
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if ((offset + size) > (SIDETIM + 1))
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panic("PCI write to SIDETIM with invalid size\n");
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} else if (offset == PCI_UDMA33_CTRL) {
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offset -= PCI_UDMA33_CTRL;
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offset += UDMACTL;
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if ((offset + size) > (UDMACTL + 1))
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panic("PCI write to UDMACTL with invalid size\n");
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} else if (offset >= PCI_UDMA33_TIMING &&
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offset < (PCI_UDMA33_TIMING + 2)) {
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offset -= PCI_UDMA33_TIMING;
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offset += UDMATIM;
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if ((offset + size) > (UDMATIM + 2))
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panic("PCI write to UDMATIM with invalid size\n");
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} else {
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panic("PCI write to unimplemented register: %x\n", offset);
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}
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memcpy((void *)&pci_regs[offset], (void *)&data, size);
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}
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// Catch the writes to specific PCI registers that have side affects
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// (like updating the PIO ranges)
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switch (offset) {
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case PCI_COMMAND:
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if (config.data[offset] & IOSE)
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io_enabled = true;
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else
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io_enabled = false;
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if (config.data[offset] & BME)
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bm_enabled = true;
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else
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bm_enabled = false;
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break;
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case PCI0_BASE_ADDR0:
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if (BARAddrs[0] != 0) {
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pri_cmd_addr = BARAddrs[0];
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if (pioInterface)
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pioInterface->addAddrRange(pri_cmd_addr,
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pri_cmd_addr + pri_cmd_size - 1);
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pri_cmd_addr &= PA_UNCACHED_MASK;
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}
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break;
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case PCI0_BASE_ADDR1:
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if (BARAddrs[1] != 0) {
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pri_ctrl_addr = BARAddrs[1];
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if (pioInterface)
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pioInterface->addAddrRange(pri_ctrl_addr,
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pri_ctrl_addr + pri_ctrl_size - 1);
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pri_ctrl_addr &= PA_UNCACHED_MASK;
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}
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break;
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case PCI0_BASE_ADDR2:
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if (BARAddrs[2] != 0) {
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sec_cmd_addr = BARAddrs[2];
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if (pioInterface)
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pioInterface->addAddrRange(sec_cmd_addr,
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sec_cmd_addr + sec_cmd_size - 1);
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sec_cmd_addr &= PA_UNCACHED_MASK;
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}
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break;
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case PCI0_BASE_ADDR3:
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if (BARAddrs[3] != 0) {
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sec_ctrl_addr = BARAddrs[3];
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if (pioInterface)
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pioInterface->addAddrRange(sec_ctrl_addr,
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sec_ctrl_addr + sec_ctrl_size - 1);
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sec_ctrl_addr &= PA_UNCACHED_MASK;
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}
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break;
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case PCI0_BASE_ADDR4:
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if (BARAddrs[4] != 0) {
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bmi_addr = BARAddrs[4];
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if (pioInterface)
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pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
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bmi_addr &= PA_UNCACHED_MASK;
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}
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break;
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}
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}
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Fault
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IdeController::read(MemReqPtr &req, uint8_t *data)
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{
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Addr offset;
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bool primary;
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bool byte;
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bool cmdBlk;
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RegType_t type;
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int disk;
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parseAddr(req->paddr, offset, primary, type);
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byte = (req->size == sizeof(uint8_t)) ? true : false;
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cmdBlk = (type == COMMAND_BLOCK) ? true : false;
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if (!io_enabled)
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return No_Fault;
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// sanity check the size (allows byte, word, or dword access)
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if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) &&
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req->size != sizeof(uint32_t))
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panic("IDE controller read of invalid size: %#x\n", req->size);
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if (type != BMI_BLOCK) {
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assert(req->size != sizeof(uint32_t));
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disk = getDisk(primary);
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if (disks[disk])
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disks[disk]->read(offset, byte, cmdBlk, data);
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} else {
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memcpy((void *)data, &bmi_regs[offset], req->size);
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}
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DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n",
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offset, req->size, *(uint32_t *)data);
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return No_Fault;
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}
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Fault
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IdeController::write(MemReqPtr &req, const uint8_t *data)
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{
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Addr offset;
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bool primary;
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bool byte;
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bool cmdBlk;
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RegType_t type;
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int disk;
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parseAddr(req->paddr, offset, primary, type);
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byte = (req->size == sizeof(uint8_t)) ? true : false;
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cmdBlk = (type == COMMAND_BLOCK) ? true : false;
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DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n",
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offset, req->size, *(uint32_t *)data);
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uint8_t oldVal, newVal;
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if (!io_enabled)
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return No_Fault;
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if (type == BMI_BLOCK && !bm_enabled)
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return No_Fault;
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if (type != BMI_BLOCK) {
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// shadow the dev bit
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if (type == COMMAND_BLOCK && offset == IDE_SELECT_OFFSET) {
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uint8_t *devBit = (primary ? &dev[0] : &dev[1]);
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*devBit = ((*data & IDE_SELECT_DEV_BIT) ? 1 : 0);
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}
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assert(req->size != sizeof(uint32_t));
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disk = getDisk(primary);
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if (disks[disk])
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disks[disk]->write(offset, byte, cmdBlk, data);
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} else {
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switch (offset) {
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// Bus master IDE command register
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case BMIC1:
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case BMIC0:
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if (req->size != sizeof(uint8_t))
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panic("Invalid BMIC write size: %x\n", req->size);
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// select the current disk based on DEV bit
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disk = getDisk(primary);
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oldVal = bmi_regs[offset];
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newVal = *data;
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// if a DMA transfer is in progress, R/W control cannot change
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if (oldVal & SSBM) {
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if ((oldVal & RWCON) ^ (newVal & RWCON)) {
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(oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON;
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}
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}
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// see if the start/stop bit is being changed
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if ((oldVal & SSBM) ^ (newVal & SSBM)) {
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if (oldVal & SSBM) {
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// stopping DMA transfer
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DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
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// clear the BMIDEA bit
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bmi_regs[offset + 0x2] &= ~BMIDEA;
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if (disks[disk] == NULL)
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panic("DMA stop for disk %d which does not exist\n",
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disk);
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// inform the disk of the DMA transfer abort
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disks[disk]->abortDma();
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} else {
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// starting DMA transfer
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|
DPRINTF(IdeCtrl, "Starting DMA transfer\n");
|
|
|
|
// set the BMIDEA bit
|
|
bmi_regs[offset + 0x2] |= BMIDEA;
|
|
|
|
if (disks[disk] == NULL)
|
|
panic("DMA start for disk %d which does not exist\n",
|
|
disk);
|
|
|
|
// inform the disk of the DMA transfer start
|
|
if (primary)
|
|
disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP0]);
|
|
else
|
|
disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP1]);
|
|
}
|
|
}
|
|
|
|
// update the register value
|
|
bmi_regs[offset] = newVal;
|
|
break;
|
|
|
|
// Bus master IDE status register
|
|
case BMIS0:
|
|
case BMIS1:
|
|
if (req->size != sizeof(uint8_t))
|
|
panic("Invalid BMIS write size: %x\n", req->size);
|
|
|
|
oldVal = bmi_regs[offset];
|
|
newVal = *data;
|
|
|
|
// the BMIDEA bit is RO
|
|
newVal |= (oldVal & BMIDEA);
|
|
|
|
// to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
|
|
if ((oldVal & IDEINTS) && (newVal & IDEINTS))
|
|
newVal &= ~IDEINTS; // clear the interrupt?
|
|
else
|
|
(oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS;
|
|
|
|
if ((oldVal & IDEDMAE) && (newVal & IDEDMAE))
|
|
newVal &= ~IDEDMAE;
|
|
else
|
|
(oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE;
|
|
|
|
bmi_regs[offset] = newVal;
|
|
break;
|
|
|
|
// Bus master IDE descriptor table pointer register
|
|
case BMIDTP0:
|
|
case BMIDTP1:
|
|
if (req->size != sizeof(uint32_t))
|
|
panic("Invalid BMIDTP write size: %x\n", req->size);
|
|
|
|
*(uint32_t *)&bmi_regs[offset] = *(uint32_t *)data & ~0x3;
|
|
break;
|
|
|
|
default:
|
|
if (req->size != sizeof(uint8_t) &&
|
|
req->size != sizeof(uint16_t) &&
|
|
req->size != sizeof(uint32_t))
|
|
panic("IDE controller write of invalid write size: %x\n",
|
|
req->size);
|
|
|
|
// do a default copy of data into the registers
|
|
memcpy((void *)&bmi_regs[offset], data, req->size);
|
|
}
|
|
}
|
|
|
|
return No_Fault;
|
|
}
|
|
|
|
////
|
|
// Serialization
|
|
////
|
|
|
|
void
|
|
IdeController::serialize(std::ostream &os)
|
|
{
|
|
// Serialize the PciDev base class
|
|
PciDev::serialize(os);
|
|
|
|
// Serialize register addresses and sizes
|
|
SERIALIZE_SCALAR(pri_cmd_addr);
|
|
SERIALIZE_SCALAR(pri_cmd_size);
|
|
SERIALIZE_SCALAR(pri_ctrl_addr);
|
|
SERIALIZE_SCALAR(pri_ctrl_size);
|
|
SERIALIZE_SCALAR(sec_cmd_addr);
|
|
SERIALIZE_SCALAR(sec_cmd_size);
|
|
SERIALIZE_SCALAR(sec_ctrl_addr);
|
|
SERIALIZE_SCALAR(sec_ctrl_size);
|
|
SERIALIZE_SCALAR(bmi_addr);
|
|
SERIALIZE_SCALAR(bmi_size);
|
|
|
|
// Serialize registers
|
|
SERIALIZE_ARRAY(bmi_regs, 16);
|
|
SERIALIZE_ARRAY(dev, 2);
|
|
SERIALIZE_ARRAY(pci_regs, 8);
|
|
|
|
// Serialize internal state
|
|
SERIALIZE_SCALAR(io_enabled);
|
|
SERIALIZE_SCALAR(bm_enabled);
|
|
SERIALIZE_ARRAY(cmd_in_progress, 4);
|
|
}
|
|
|
|
void
|
|
IdeController::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
// Unserialize the PciDev base class
|
|
PciDev::unserialize(cp, section);
|
|
|
|
// Unserialize register addresses and sizes
|
|
UNSERIALIZE_SCALAR(pri_cmd_addr);
|
|
UNSERIALIZE_SCALAR(pri_cmd_size);
|
|
UNSERIALIZE_SCALAR(pri_ctrl_addr);
|
|
UNSERIALIZE_SCALAR(pri_ctrl_size);
|
|
UNSERIALIZE_SCALAR(sec_cmd_addr);
|
|
UNSERIALIZE_SCALAR(sec_cmd_size);
|
|
UNSERIALIZE_SCALAR(sec_ctrl_addr);
|
|
UNSERIALIZE_SCALAR(sec_ctrl_size);
|
|
UNSERIALIZE_SCALAR(bmi_addr);
|
|
UNSERIALIZE_SCALAR(bmi_size);
|
|
|
|
// Unserialize registers
|
|
UNSERIALIZE_ARRAY(bmi_regs, 16);
|
|
UNSERIALIZE_ARRAY(dev, 2);
|
|
UNSERIALIZE_ARRAY(pci_regs, 8);
|
|
|
|
// Unserialize internal state
|
|
UNSERIALIZE_SCALAR(io_enabled);
|
|
UNSERIALIZE_SCALAR(bm_enabled);
|
|
UNSERIALIZE_ARRAY(cmd_in_progress, 4);
|
|
}
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
|
|
|
|
SimObjectParam<IntrControl *> intr_ctrl;
|
|
SimObjectVectorParam<IdeDisk *> disks;
|
|
SimObjectParam<MemoryController *> mmu;
|
|
SimObjectParam<PciConfigAll *> configspace;
|
|
SimObjectParam<PciConfigData *> configdata;
|
|
SimObjectParam<Tsunami *> tsunami;
|
|
Param<uint32_t> pci_bus;
|
|
Param<uint32_t> pci_dev;
|
|
Param<uint32_t> pci_func;
|
|
SimObjectParam<Bus *> host_bus;
|
|
SimObjectParam<HierParams *> hier;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
|
|
|
|
INIT_PARAM(intr_ctrl, "Interrupt Controller"),
|
|
INIT_PARAM(disks, "IDE disks attached to this controller"),
|
|
INIT_PARAM(mmu, "Memory controller"),
|
|
INIT_PARAM(configspace, "PCI Configspace"),
|
|
INIT_PARAM(configdata, "PCI Config data"),
|
|
INIT_PARAM(tsunami, "Tsunami chipset pointer"),
|
|
INIT_PARAM(pci_bus, "PCI bus ID"),
|
|
INIT_PARAM(pci_dev, "PCI device number"),
|
|
INIT_PARAM(pci_func, "PCI function code"),
|
|
INIT_PARAM_DFLT(host_bus, "Host bus to attach to", NULL),
|
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(IdeController)
|
|
|
|
CREATE_SIM_OBJECT(IdeController)
|
|
{
|
|
return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
|
|
configspace, configdata, tsunami, pci_bus,
|
|
pci_dev, pci_func, host_bus, hier);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("IdeController", IdeController)
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|