8e4ec55703
arch/alpha/arguments.cc: Renamed readFloatRegInt to readFloatRegBits arch/alpha/ev5.cc: Removed the Double from setFloatRegDouble arch/alpha/registerfile.hh: Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC. arch/alpha/types.hh: Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register. arch/isa_parser.py: Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg. base/remote_gdb.cc: kern/tru64/tru64.hh: Replaced setFloatRegInt with setFloatRegBits cpu/cpu_exec_context.cc: Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits. cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/regfile.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.hh: Implemented the new versions of the floating point read and set functions. cpu/simple/cpu.cc: Replaced setFloatRegDouble with setFloatReg --HG-- extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
299 lines
9.3 KiB
C++
299 lines
9.3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_CPU_REGFILE_HH__
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#define __CPU_O3_CPU_REGFILE_HH__
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// @todo: Destructor
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#include "arch/isa_traits.hh"
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#include "arch/faults.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/o3/comm.hh"
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#if FULL_SYSTEM
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#include "kern/kernel_stats.hh"
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#endif
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// This really only depends on the ISA, and not the Impl. It might be nicer
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// to see if I can make it depend on nothing...
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// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
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// and should go in the AlphaFullCPU.
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template <class Impl>
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class PhysRegFile
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{
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protected:
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::MiscRegFile MiscRegFile;
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typedef TheISA::MiscReg MiscReg;
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//Note that most of the definitions of the IntReg, FloatReg, etc. exist
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//within the Impl/ISA class and not within this PhysRegFile class.
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//Will need some way to allow stuff like swap_palshadow to access the
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//correct registers. Might require code changes to swap_palshadow and
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//other execution contexts.
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//Will make these registers public for now, but they probably should
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//be private eventually with some accessor functions.
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public:
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typedef typename Impl::FullCPU FullCPU;
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PhysRegFile(unsigned _numPhysicalIntRegs,
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unsigned _numPhysicalFloatRegs);
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//Everything below should be pretty well identical to the normal
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//register file that exists within AlphaISA class.
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//The duplication is unfortunate but it's better than having
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//different ways to access certain registers.
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//Add these in later when everything else is in place
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// void serialize(std::ostream &os);
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// void unserialize(Checkpoint *cp, const std::string §ion);
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uint64_t readIntReg(PhysRegIndex reg_idx)
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{
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assert(reg_idx < numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Access to int register %i, has data "
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"%i\n", int(reg_idx), intRegFile[reg_idx]);
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return intRegFile[reg_idx];
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}
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FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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FloatReg floatReg = floatRegFile.readReg(reg_idx, width);
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DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
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"data %8.8d\n", int(reg_idx), (double)floatReg);
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return floatReg;
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}
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FloatReg readFloatReg(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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FloatReg floatReg = floatRegFile.readReg(reg_idx);
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DPRINTF(IEW, "RegFile: Access to float register %i, has "
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"data %8.8d\n", int(reg_idx), (double)floatReg);
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return floatReg;
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}
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FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width);
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DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, "
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"has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
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return floatRegBits;
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}
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FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx);
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DPRINTF(IEW, "RegFile: Access to float register %i as int, "
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"has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
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return floatRegBits;
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}
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void setIntReg(PhysRegIndex reg_idx, uint64_t val)
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{
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assert(reg_idx < numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n",
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int(reg_idx), val);
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intRegFile[reg_idx] = val;
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}
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void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
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int(reg_idx), (double)val);
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floatRegFile.setReg(reg_idx, val, width);
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}
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void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
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int(reg_idx), (double)val);
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floatRegFile.setReg(reg_idx, val);
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}
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void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
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int(reg_idx), (uint64_t)val);
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floatRegFile.setRegBits(reg_idx, val, width);
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}
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void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
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{
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// Remove the base Float reg dependency.
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reg_idx = reg_idx - numPhysicalIntRegs;
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assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
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DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
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int(reg_idx), (uint64_t)val);
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floatRegFile.setRegBits(reg_idx, val);
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}
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uint64_t readPC()
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{
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return pc;
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}
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void setPC(uint64_t val)
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{
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pc = val;
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}
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void setNextPC(uint64_t val)
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{
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npc = val;
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}
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//Consider leaving this stuff and below in some implementation specific
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//file as opposed to the general register file. Or have a derived class.
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MiscReg readMiscReg(int misc_reg)
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{
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// Dummy function for now.
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// @todo: Fix this once proxy XC is used.
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return 0;
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}
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Fault setMiscReg(int misc_reg, const MiscReg &val)
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{
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// Dummy function for now.
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// @todo: Fix this once proxy XC is used.
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return NoFault;
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}
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#if FULL_SYSTEM
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int readIntrFlag() { return intrflag; }
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void setIntrFlag(int val) { intrflag = val; }
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#endif
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// These should be private eventually, but will be public for now
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// so that I can hack around the initregs issue.
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public:
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/** (signed) integer register file. */
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IntReg *intRegFile;
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/** Floating point register file. */
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FloatReg *floatRegFile;
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/** Miscellaneous register file. */
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MiscRegFile miscRegs;
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/** Program counter. */
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Addr pc;
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/** Next-cycle program counter. */
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Addr npc;
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#if FULL_SYSTEM
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private:
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// This is ISA specifc stuff; remove it eventually once ISAImpl is used
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// IntReg palregs[NumIntRegs]; // PAL shadow registers
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int intrflag; // interrupt flag
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bool pal_shadow; // using pal_shadow registers
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#endif
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private:
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FullCPU *cpu;
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public:
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void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; }
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unsigned numPhysicalIntRegs;
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unsigned numPhysicalFloatRegs;
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};
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template <class Impl>
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PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
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unsigned _numPhysicalFloatRegs)
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: numPhysicalIntRegs(_numPhysicalIntRegs),
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numPhysicalFloatRegs(_numPhysicalFloatRegs)
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{
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intRegFile = new IntReg[numPhysicalIntRegs];
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floatRegFile = new FloatReg[numPhysicalFloatRegs];
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memset(intRegFile, 0, sizeof(*intRegFile));
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memset(floatRegFile, 0, sizeof(*floatRegFile));
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}
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#endif // __CPU_O3_CPU_REGFILE_HH__
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