207 lines
23 KiB
Text
207 lines
23 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 924480 # Simulator instruction rate (inst/s)
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host_mem_usage 209588 # Number of bytes of host memory used
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host_seconds 1617.88 # Real time elapsed on the host
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host_tick_rate 1064572030 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1495700470 # Number of instructions simulated
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sim_seconds 1.722353 # Number of seconds simulated
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sim_ticks 1722352562000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 382375369 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 149160200 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 147694052 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 210.782575 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 530069421 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 530069421 # number of overall hits
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system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3192961 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 2513875 # number of replacements
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system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4086.831173 # Cycle average of tags in use
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system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 8217762000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 1463913 # number of writebacks
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system.cpu.icache.ReadReq_accesses 1068347073 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 48417.910448 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 45417.910448 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1068344259 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 136248000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 127806000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 379653.254797 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1068347073 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 48417.910448 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 45417.910448 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1068344259 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 136248000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
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system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 127806000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 1068347073 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 48417.910448 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 45417.910448 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1068344259 # number of overall hits
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system.cpu.icache.overall_miss_latency 136248000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
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system.cpu.icache.overall_misses 2814 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 127806000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 1253 # number of replacements
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system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 887.487990 # Cycle average of tags in use
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system.cpu.icache.total_refs 1068344259 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 1729627 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 21815196000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 419523 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 16780920000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 419523 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 3.428066 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 2520785 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 62955423500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 1210681 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 48427240000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 1210681 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 2520785 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 1310104 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 62955423500 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 1210681 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 48427240000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 1210681 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 663513 # number of replacements
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system.cpu.l2cache.sampled_refs 679921 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 17216.037197 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 921771494000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 481430 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 3444705124 # number of cpu cycles simulated
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system.cpu.num_insts 1495700470 # Number of instructions executed
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system.cpu.num_refs 533262337 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
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---------- End Simulation Statistics ----------
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