3bfb59f70d
mappings (writes still unverified, and read could probably be looked over
a bit more too)
dev/ide_disk.cc:
dev/ide_disk.hh:
Major changes to fix bogus handling of dma transfers. The read seems to
work pretty well, but the write is unverfied until we can get a disk
image that actually tries to write.
dev/tsunami_pchip.cc:
Change mask to properly mask 13 bits not 12
--HG--
extra : convert_revision : 08fe9bc32970e449cd045de479553a96a4e389d6
319 lines
10 KiB
C++
319 lines
10 KiB
C++
/* $Id$ */
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/* @file
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* Tsunami PChip (pci)
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/console.hh"
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#include "dev/etherdev.hh"
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#include "dev/scsi_ctrl.hh"
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#include "dev/tlaser_clock.hh"
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#include "dev/tsunami_pchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "mem/functional_mem/physical_memory.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
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MemoryController *mmu)
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: FunctionalMemory(name), addr(a), tsunami(t)
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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for (int i = 0; i < 4; i++) {
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wsba[i] = 0;
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wsm[i] = 0;
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tba[i] = 0;
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}
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//Set back pointer in tsunami
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tsunami->pchip = this;
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}
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Fault
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TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
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// ExecContext *xc = req->xc;
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// int cpuid = xc->cpu_id;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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*(uint64_t*)data = wsba[0];
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return No_Fault;
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case TSDEV_PC_WSBA1:
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*(uint64_t*)data = wsba[1];
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return No_Fault;
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case TSDEV_PC_WSBA2:
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*(uint64_t*)data = wsba[2];
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return No_Fault;
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case TSDEV_PC_WSBA3:
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*(uint64_t*)data = wsba[3];
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return No_Fault;
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case TSDEV_PC_WSM0:
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*(uint64_t*)data = wsm[0];
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return No_Fault;
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case TSDEV_PC_WSM1:
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*(uint64_t*)data = wsm[1];
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return No_Fault;
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case TSDEV_PC_WSM2:
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*(uint64_t*)data = wsm[2];
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return No_Fault;
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case TSDEV_PC_WSM3:
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*(uint64_t*)data = wsm[3];
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return No_Fault;
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case TSDEV_PC_TBA0:
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*(uint64_t*)data = tba[0];
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return No_Fault;
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case TSDEV_PC_TBA1:
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*(uint64_t*)data = tba[1];
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return No_Fault;
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case TSDEV_PC_TBA2:
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*(uint64_t*)data = tba[2];
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return No_Fault;
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case TSDEV_PC_TBA3:
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*(uint64_t*)data = tba[3];
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return No_Fault;
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case TSDEV_PC_PCTL:
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// might want to change the clock??
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*(uint64_t*)data = 0x00; // try this
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return No_Fault;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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panic("PC_PERROR not implemented\n");
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case TSDEV_PC_PERRMASK:
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panic("PC_PERRMASK not implemented\n");
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
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return No_Fault;
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n\n");
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}
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DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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Fault
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TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
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{
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DPRINTF(Tsunami, "write - va=%#x size=%d \n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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wsba[0] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSBA1:
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wsba[1] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSBA2:
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wsba[2] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSBA3:
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wsba[3] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM0:
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wsm[0] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM1:
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wsm[1] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM2:
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wsm[2] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM3:
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wsm[3] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA0:
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tba[0] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA1:
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tba[1] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA2:
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tba[2] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA3:
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tba[3] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_PCTL:
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// might want to change the clock??
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//*(uint64_t*)data; // try this
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return No_Fault;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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panic("PC_PERROR not implemented\n");
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case TSDEV_PC_PERRMASK:
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panic("PC_PERRMASK not implemented\n");
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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return No_Fault; // value ignored, supposted to invalidate SG TLB
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n\n");
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}
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DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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#define DMA_ADDR_MASK ULL(0x3ffffffff)
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Addr
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TsunamiPChip::translatePciToDma(Addr busAddr)
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{
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// compare the address to the window base registers
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uint64_t tbaMask = 0;
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uint64_t baMask = 0;
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uint64_t windowMask = 0;
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uint64_t windowBase = 0;
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uint64_t pteEntry = 0;
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Addr pteAddr;
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Addr dmaAddr;
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for (int i = 0; i < 4; i++) {
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windowBase = wsba[i];
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windowMask = ~wsm[i] & (0x7ff << 20);
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if ((busAddr & windowMask) == (windowBase & windowMask)) {
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if (wsba[i] & 0x1) { // see if enabled
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if (wsba[i] & 0x2) { // see if SG bit is set
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/** @todo
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This currently is faked by just doing a direct
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read from memory, however, to be realistic, this
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needs to actually do a bus transaction. The process
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is explained in the tsunami documentation on page
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10-12 and basically munges the address to look up a
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PTE from a table in memory and then uses that mapping
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to create an address for the SG page
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*/
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tbaMask = ~(((wsm[i] & (0x7ff << 20)) >> 10) | 0x3ff);
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baMask = (wsm[i] & (0x7ff << 20)) | (0x7f << 13);
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pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
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memcpy((void *)&pteEntry,
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tsunami->system->
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physmem->dma_addr(pteAddr, sizeof(uint64_t)),
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sizeof(uint64_t));
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dmaAddr = ((pteEntry & ~0x1) << 12) | (busAddr & 0x1fff);
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} else {
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baMask = (wsm[i] & (0x7ff << 20)) | 0xfffff;
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tbaMask = ~baMask;
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dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
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}
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return (dmaAddr & DMA_ADDR_MASK);
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}
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}
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}
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return 0;
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}
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void
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TsunamiPChip::serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(wsba, 4);
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SERIALIZE_ARRAY(wsm, 4);
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SERIALIZE_ARRAY(tba, 4);
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}
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void
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TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(wsba, 4);
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UNSERIALIZE_ARRAY(wsm, 4);
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UNSERIALIZE_ARRAY(tba, 4);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
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SimObjectParam<Tsunami *> tsunami;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
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INIT_PARAM(tsunami, "Tsunami"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address")
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END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
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CREATE_SIM_OBJECT(TsunamiPChip)
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{
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return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu);
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}
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REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
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