sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

538 lines
60 KiB
Text
Raw Blame History

---------- Begin Simulation Statistics ----------
sim_seconds 2.623057 # Number of seconds simulated
sim_ticks 2623057163500 # Number of ticks simulated
final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1251674 # Simulator instruction rate (inst/s)
host_op_rate 1251674 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1804181213 # Simulator tick rate (ticks/s)
host_mem_usage 294596 # Number of bytes of host memory used
host_seconds 1453.88 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory
system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory
system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 19568 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 47613206 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 47632774 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 19568 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 19568 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 24934862 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 24934862 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 24934862 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 19568 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47613206 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 72567635 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.itb.fetch_hits 1826378510 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 5246114327 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
system.cpu.num_int_insts 1725565901 # number of integer instructions
system.cpu.num_fp_insts 805526 # number of float instructions
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
system.cpu.num_mem_refs 611922547 # number of memory refs
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5246114327 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 214632552 # Number of branches fetched
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction
system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction
system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction
system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction
system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1826378509 # Class of executed instruction
system.cpu.dcache.tags.replacements 9107638 # number of replacements
system.cpu.dcache.tags.tagsinuse 4079.260769 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 40977438500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.260769 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995913 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995913 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143001525000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 143001525000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57421337000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 57421337000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 200422862000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 200422862000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 200422862000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 200422862000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19799.685396 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19799.685396 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30392.594690 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30392.594690 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 21996.127411 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21996.127411 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks
system.cpu.dcache.writebacks::total 3679426 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135779111000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 135779111000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55532017000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 55532017000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191311128000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 191311128000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191311128000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 191311128000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18799.685396 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18799.685396 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29392.594690 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29392.594690 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1 # number of replacements
system.cpu.icache.tags.tagsinuse 612.447387 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 612.447387 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.299047 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.299047 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses
system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits
system.cpu.icache.overall_hits::total 1826377708 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
system.cpu.icache.overall_misses::total 802 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44163500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 44163500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 44163500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 44163500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 44163500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 44163500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.708229 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55066.708229 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55066.708229 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55066.708229 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43361500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 43361500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43361500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 43361500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43361500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 43361500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54066.708229 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54066.708229 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 1919524 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30534.757407 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1949316 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.377078 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 218167130000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15101.273798 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.972607 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15394.511002 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.460854 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001189 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.469803 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.931847 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1062 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27300 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 149600036 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 149600036 # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks 3679426 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3679426 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1106935 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1106935 # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6053359 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6053359 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 7160294 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7160294 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 7160294 # number of overall hits
system.cpu.l2cache.overall_hits::total 7160294 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 782385 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 782385 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 802 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 802 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1169055 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1169055 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1951440 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1952242 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1951440 # number of overall misses
system.cpu.l2cache.overall_misses::total 1952242 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41075219500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 41075219500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 42150500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 42150500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61385220500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 61385220500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 42150500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 102460440000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 102502590500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 42150500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 102460440000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 102502590500 # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks 3679426 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3679426 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222414 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7222414 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414109 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414109 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161865 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161865 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214168 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.214237 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214168 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.214237 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.008947 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.008947 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52556.733167 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52556.733167 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52508.411067 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52508.411067 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52505.063665 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52505.063665 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks
system.cpu.l2cache.writebacks::total 1021962 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782385 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 782385 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1169055 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1169055 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951440 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1952242 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951440 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1952242 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33251369500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33251369500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34130500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34130500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49694670500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49694670500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34130500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82946040000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 82980170500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34130500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82946040000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 82980170500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414109 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161865 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161865 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.008947 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.008947 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42556.733167 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42556.733167 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42508.411067 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42508.411067 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 4701388 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1919524 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.095310 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.293643 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 18220175 90.47% 90.47% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 1919524 9.53% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1169857 # Transaction distribution
system.membus.trans_dist::Writeback 1021962 # Transaction distribution
system.membus.trans_dist::CleanEvict 896683 # Transaction distribution
system.membus.trans_dist::ReadExReq 782385 # Transaction distribution
system.membus.trans_dist::ReadExResp 782385 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3872712 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 3872712 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 3872712 # Request fanout histogram
system.membus.reqLayer0.occupancy 7960873524 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 9761522024 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
Reference in a new issue View git blame Copy permalink