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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Steve Reinhardt f5d1dd75e5 stats: overdue updates to long regressions
2016-03-16 13:03:49 -07:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.837475 # Number of seconds simulated
sim_ticks 2837474672000 # Number of ticks simulated
final_tick 2837474672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 80224 # Simulator instruction rate (inst/s)
host_op_rate 97291 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1891605778 # Simulator tick rate (ticks/s)
host_mem_usage 603308 # Number of bytes of host memory used
host_seconds 1500.04 # Real time elapsed on the host
sim_insts 120338385 # Number of instructions simulated
sim_ops 145939190 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1300544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1269544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8448640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 171296 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 573268 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 376832 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 12143260 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1300544 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 171296 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1471840 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8572864 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8590428 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 22568 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 20357 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 132010 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2744 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 8978 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 5888 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 192594 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 133951 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 138342 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 458346 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 447420 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2977521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 68 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 60369 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 202035 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 132805 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4279601 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 458346 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 60369 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 518715 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3021301 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3027491 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3021301 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 458346 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 453596 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2977521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 60369 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 202049 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 132805 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7307092 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 192595 # Number of read requests accepted
system.physmem.writeReqs 138342 # Number of write requests accepted
system.physmem.readBursts 192595 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 138342 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12315840 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue
system.physmem.bytesWritten 8603136 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12143324 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8590428 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11930 # Per bank write bursts
system.physmem.perBankRdBursts::1 11054 # Per bank write bursts
system.physmem.perBankRdBursts::2 12038 # Per bank write bursts
system.physmem.perBankRdBursts::3 12107 # Per bank write bursts
system.physmem.perBankRdBursts::4 14171 # Per bank write bursts
system.physmem.perBankRdBursts::5 12096 # Per bank write bursts
system.physmem.perBankRdBursts::6 12498 # Per bank write bursts
system.physmem.perBankRdBursts::7 12306 # Per bank write bursts
system.physmem.perBankRdBursts::8 12126 # Per bank write bursts
system.physmem.perBankRdBursts::9 12003 # Per bank write bursts
system.physmem.perBankRdBursts::10 11820 # Per bank write bursts
system.physmem.perBankRdBursts::11 10972 # Per bank write bursts
system.physmem.perBankRdBursts::12 11787 # Per bank write bursts
system.physmem.perBankRdBursts::13 12524 # Per bank write bursts
system.physmem.perBankRdBursts::14 11749 # Per bank write bursts
system.physmem.perBankRdBursts::15 11254 # Per bank write bursts
system.physmem.perBankWrBursts::0 8457 # Per bank write bursts
system.physmem.perBankWrBursts::1 8003 # Per bank write bursts
system.physmem.perBankWrBursts::2 8794 # Per bank write bursts
system.physmem.perBankWrBursts::3 8731 # Per bank write bursts
system.physmem.perBankWrBursts::4 8108 # Per bank write bursts
system.physmem.perBankWrBursts::5 8557 # Per bank write bursts
system.physmem.perBankWrBursts::6 8913 # Per bank write bursts
system.physmem.perBankWrBursts::7 8687 # Per bank write bursts
system.physmem.perBankWrBursts::8 8491 # Per bank write bursts
system.physmem.perBankWrBursts::9 8422 # Per bank write bursts
system.physmem.perBankWrBursts::10 8472 # Per bank write bursts
system.physmem.perBankWrBursts::11 8088 # Per bank write bursts
system.physmem.perBankWrBursts::12 8500 # Per bank write bursts
system.physmem.perBankWrBursts::13 8546 # Per bank write bursts
system.physmem.perBankWrBursts::14 8126 # Per bank write bursts
system.physmem.perBankWrBursts::15 7529 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 17 # Number of times write queue was full causing retry
system.physmem.totGap 2837474405000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 551 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 3086 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 188930 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 133951 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 61287 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 73690 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 12995 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10046 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8300 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7163 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 6190 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4461 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1302 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 831 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 561 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 262 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2593 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3637 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4815 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4517 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5656 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5607 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6028 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6710 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7608 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7727 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8537 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9655 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8905 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9626 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 11825 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 9219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8077 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1366 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 492 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 86799 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 241.004067 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 135.845956 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 303.218552 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 46693 53.79% 53.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 16731 19.28% 73.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5770 6.65% 79.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3383 3.90% 83.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2638 3.04% 86.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1583 1.82% 88.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 983 1.13% 89.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 925 1.07% 90.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8093 9.32% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 86799 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6476 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 29.714330 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 577.856758 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6474 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6476 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6476 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.757258 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.913805 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.667335 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5315 82.07% 82.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 506 7.81% 89.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 87 1.34% 91.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 43 0.66% 91.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 52 0.80% 92.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 25 0.39% 93.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 59 0.91% 93.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 16 0.25% 94.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 114 1.76% 96.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 13 0.20% 96.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 11 0.17% 96.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 13 0.20% 96.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 75 1.16% 97.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 2 0.03% 97.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 5 0.08% 97.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 24 0.37% 98.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 82 1.27% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 2 0.03% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 3 0.05% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 3 0.05% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 2 0.03% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 6 0.09% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 6 0.09% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6476 # Writes before turning the bus around for reads
system.physmem.totQLat 6262539288 # Total ticks spent queuing
system.physmem.totMemAccLat 9870695538 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 962175000 # Total ticks spent in databus transfers
system.physmem.avgQLat 32543.66 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 51293.66 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.34 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.03 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.28 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.03 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.64 # Average write queue length when enqueuing
system.physmem.readRowHits 160629 # Number of row buffer hits during reads
system.physmem.writeRowHits 79430 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes
system.physmem.avgGap 8574062.15 # Average gap between requests
system.physmem.pageHitRate 73.44 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 333396000 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 181912500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 765952200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 442260000 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 185329943760 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 80518312575 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1631853855750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1899425632785 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.407413 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2714633882248 # Time in different power states
system.physmem_0.memoryStateTime::REF 94749460000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 28091326752 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 322804440 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 176133375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 735033000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 428807520 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 185329943760 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 80062823295 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1632253407750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1899308953140 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.366292 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2715300909163 # Time in different power states
system.physmem_1.memoryStateTime::REF 94749460000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 27422902087 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 53970528 # Number of BP lookups
system.cpu0.branchPred.condPredicted 25026545 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1030924 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 32677551 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 24281541 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 74.306489 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 15568765 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 33847 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 71872 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 71872 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26693 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21064 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 24115 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 47757 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 506.909982 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 3155.228311 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191 46441 97.24% 97.24% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383 936 1.96% 99.20% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575 182 0.38% 99.59% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767 156 0.33% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959 14 0.03% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 47757 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 18781 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 11082.663330 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 9588.241676 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 7811.113486 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767 18652 99.31% 99.31% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 107 0.57% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 11 0.06% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.05% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 18781 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 75809851172 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.731325 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.459247 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 20539595904 27.09% 27.09% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 55205651768 72.82% 99.91% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2 30292500 0.04% 99.95% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::3 15753500 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4 4835000 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::5 2801000 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6 4041000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::7 1434000 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8 1051000 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::9 726000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10 722500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::11 355500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12 1232500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::13 309000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14 147500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::15 902500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 75809851172 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5808 79.13% 79.13% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1532 20.87% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 7340 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71872 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71872 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7340 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7340 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 79212 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 24452865 # DTB read hits
system.cpu0.dtb.read_misses 61042 # DTB read misses
system.cpu0.dtb.write_hits 18137868 # DTB write hits
system.cpu0.dtb.write_misses 10830 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3798 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 179 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2460 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 1027 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 24513907 # DTB read accesses
system.cpu0.dtb.write_accesses 18148698 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 42590733 # DTB hits
system.cpu0.dtb.misses 71872 # DTB misses
system.cpu0.dtb.accesses 42662605 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 11904 # Table walker walks requested
system.cpu0.itb.walker.walksShort 11904 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4233 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6584 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 1087 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 10817 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 600.397522 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 2698.053078 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095 10265 94.90% 94.90% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191 149 1.38% 96.27% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287 271 2.51% 98.78% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383 75 0.69% 99.47% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479 17 0.16% 99.63% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575 19 0.18% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671 9 0.08% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 10817 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 3962 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12538.112065 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11491.228550 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 5924.134206 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383 3642 91.92% 91.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767 274 6.92% 98.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151 42 1.06% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535 3 0.08% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 3962 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 19975198824 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.751864 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.432117 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 4958102500 24.82% 24.82% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 15015628824 75.17% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 1397500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 19975198824 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2530 88.00% 88.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 345 12.00% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2875 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11904 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11904 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2875 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2875 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 14779 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 74216434 # ITB inst hits
system.cpu0.itb.inst_misses 11904 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2616 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 2203 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 74228338 # ITB inst accesses
system.cpu0.itb.hits 74216434 # DTB hits
system.cpu0.itb.misses 11904 # DTB misses
system.cpu0.itb.accesses 74228338 # DTB accesses
system.cpu0.numCycles 211032659 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 21140186 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 200489800 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 53970528 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 39850306 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 180538670 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 5902720 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 164381 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 72575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 387139 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 466386 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 108060 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 74215735 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 285684 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 6141 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 205828757 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.190746 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.306340 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 98382336 47.80% 47.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 31160617 15.14% 62.94% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 14928225 7.25% 70.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 61357579 29.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 205828757 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.255745 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.950042 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 26450347 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 110999505 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 60649256 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 5136264 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2593385 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 3184080 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 362502 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 158814101 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 4185741 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 2593385 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 35368680 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 13285879 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 85120734 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 56726611 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 12733468 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 141845783 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 1133457 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1506583 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 170458 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 63498 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 8406258 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 146030033 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 654050739 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 157600072 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 10971 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 133759652 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 12270378 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 2729976 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 2583213 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 22947942 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 25466090 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 19748562 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1757357 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2684729 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 138695125 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1764118 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 136568956 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 514251 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 11572106 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 23832263 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 127429 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 205828757 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.663508 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 0.962661 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 127035634 61.72% 61.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 34468527 16.75% 78.47% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 32041551 15.57% 94.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 11114901 5.40% 99.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1168096 0.57% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 48 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 205828757 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 11115121 43.73% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 78 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5928119 23.32% 67.05% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 8376643 32.95% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 92017831 67.38% 67.38% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 112728 0.08% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 8135 0.01% 67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 25188018 18.44% 85.91% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 19239929 14.09% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 136568956 # Type of FU issued
system.cpu0.iq.rate 0.647146 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 25419961 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.186133 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 504862433 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 152038807 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 132856114 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 38448 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 13226 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 11442 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 161961537 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 25065 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 381033 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2126828 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2734 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 20764 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1086115 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 121849 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 393509 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 2593385 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1923862 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 225428 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 140668675 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 25466090 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 19748562 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 902405 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 28750 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 172587 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 20764 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 314258 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 420576 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 734834 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 135413166 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 24708809 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1084045 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 209432 # number of nop insts executed
system.cpu0.iew.exec_refs 43749631 # number of memory reference insts executed
system.cpu0.iew.exec_branches 26148134 # Number of branches executed
system.cpu0.iew.exec_stores 19040822 # Number of stores executed
system.cpu0.iew.exec_rate 0.641669 # Inst execution rate
system.cpu0.iew.wb_sent 134807850 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 132867556 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 67789134 # num instructions producing a value
system.cpu0.iew.wb_consumers 109636664 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.629607 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.618307 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 10465399 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1636689 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 672949 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 202511851 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.637192 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.338822 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 140790239 69.52% 69.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 34042188 16.81% 86.33% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 12969775 6.40% 92.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3421790 1.69% 94.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 4963486 2.45% 96.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 2698624 1.33% 98.21% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1492584 0.74% 98.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 576020 0.28% 99.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1557145 0.77% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 202511851 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 106573853 # Number of instructions committed
system.cpu0.commit.committedOps 129038976 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 42001709 # Number of memory references committed
system.cpu0.commit.loads 23339262 # Number of loads committed
system.cpu0.commit.membars 664486 # Number of memory barriers committed
system.cpu0.commit.branches 25472286 # Number of branches committed
system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 112576869 # Number of committed integer instructions.
system.cpu0.commit.function_calls 4879585 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 86918951 67.36% 67.36% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 110181 0.09% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 8135 0.01% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 23339262 18.09% 85.54% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 18662447 14.46% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 129038976 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1557145 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 317122360 # The number of ROB reads
system.cpu0.rob.rob_writes 282315709 # The number of ROB writes
system.cpu0.timesIdled 140732 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 5203902 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5463916952 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 106422010 # Number of Instructions Simulated
system.cpu0.committedOps 128887133 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.982979 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.982979 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.504292 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.504292 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 146824943 # number of integer regfile reads
system.cpu0.int_regfile_writes 83833584 # number of integer regfile writes
system.cpu0.fp_regfile_reads 9570 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes
system.cpu0.cc_regfile_reads 478163179 # number of cc regfile reads
system.cpu0.cc_regfile_writes 51330102 # number of cc regfile writes
system.cpu0.misc_regfile_reads 283152527 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1260318 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 750354 # number of replacements
system.cpu0.dcache.tags.tagsinuse 496.537127 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 38788721 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 750866 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 51.658646 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.537127 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969799 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.969799 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 83716112 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 83716112 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 22157554 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 22157554 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 15381796 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15381796 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316247 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 316247 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371104 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 371104 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369755 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 369755 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 37539350 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 37539350 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 37855597 # number of overall hits
system.cpu0.dcache.overall_hits::total 37855597 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 688529 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 688529 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1970911 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1970911 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153379 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 153379 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 26060 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 26060 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20217 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20217 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2659440 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2659440 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2812819 # number of overall misses
system.cpu0.dcache.overall_misses::total 2812819 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9958933000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 9958933000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36282173869 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 36282173869 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 417298000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 417298000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 534996000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 534996000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 601500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 601500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 46241106869 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 46241106869 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 46241106869 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 46241106869 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 22846083 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 22846083 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 17352707 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 17352707 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 469626 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 469626 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397164 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 397164 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 389972 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 389972 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 40198790 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 40198790 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 40668416 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 40668416 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030138 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.030138 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113579 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.113579 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.326598 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.326598 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065615 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065615 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051842 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051842 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066157 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.066157 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069165 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.069165 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14464.071956 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14464.071956 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18408.834224 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 18408.834224 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16012.970069 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16012.970069 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26462.679923 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26462.679923 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17387.535297 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 17387.535297 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16439.417847 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16439.417847 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 1356 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 5556289 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 211720 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 26.243572 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 750354 # number of writebacks
system.cpu0.dcache.writebacks::total 750354 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 278216 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 278216 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1634757 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1634757 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19327 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19327 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1912973 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1912973 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1912973 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1912973 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 410313 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 410313 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336154 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 336154 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107278 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 107278 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6733 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6733 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20217 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20217 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 746467 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 746467 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 853745 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 853745 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31833 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31833 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60326 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60326 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5129549000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5129549000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7629793401 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7629793401 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1790414000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1790414000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108965500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108965500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 514792000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 514792000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 588500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 588500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12759342401 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 12759342401 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14549756401 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 14549756401 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6627988500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6627988500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5396142000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5396142000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12024130500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12024130500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017960 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019372 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019372 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228433 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228433 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016953 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016953 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051842 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051842 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018569 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.018569 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020993 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.020993 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12501.551255 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12501.551255 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22697.315519 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22697.315519 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16689.479670 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16689.479670 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16183.796228 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16183.796228 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25463.322946 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25463.322946 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17092.975846 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17092.975846 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17042.274217 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17042.274217 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208211.243050 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208211.243050 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189384.831362 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189384.831362 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199319.207307 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199319.207307 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1310036 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.377310 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 72844625 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1310548 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 55.583332 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 8206989500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.377310 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998784 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998784 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 149734646 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 149734646 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 72844625 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 72844625 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 72844625 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 72844625 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 72844625 # number of overall hits
system.cpu0.icache.overall_hits::total 72844625 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1367409 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1367409 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1367409 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1367409 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1367409 # number of overall misses
system.cpu0.icache.overall_misses::total 1367409 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14971096575 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14971096575 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14971096575 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14971096575 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14971096575 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14971096575 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 74212034 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 74212034 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 74212034 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 74212034 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 74212034 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 74212034 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018426 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.018426 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018426 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.018426 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018426 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.018426 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.513996 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.513996 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.513996 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10948.513996 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.513996 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10948.513996 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 2032759 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 1838 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 126344 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 17 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.089082 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 108.117647 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 1310036 # number of writebacks
system.cpu0.icache.writebacks::total 1310036 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56829 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 56829 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 56829 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 56829 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 56829 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 56829 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1310580 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1310580 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1310580 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1310580 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1310580 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1310580 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13438912548 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 13438912548 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13438912548 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 13438912548 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13438912548 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 13438912548 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420651998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420651998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420651998 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 420651998 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017660 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.017660 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.017660 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10254.171854 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10254.171854 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10254.171854 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10254.171854 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10254.171854 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10254.171854 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1920802 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1923636 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 2578 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 246404 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 284549 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16107.526172 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 3421842 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 300696 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 11.379739 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14704.444531 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.370488 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.981842 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1389.729311 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.897488 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000755 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000060 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.084822 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.983125 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 962 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15179 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 421 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 202 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 491 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4664 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7779 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2114 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058716 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.926453 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 69504946 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 69504946 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60895 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14710 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 75605 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 504685 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 504685 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 1522610 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 1522610 # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205303 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 205303 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1254795 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1254795 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 426557 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 426557 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60895 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14710 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1254795 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 631860 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1962260 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60895 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14710 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1254795 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 631860 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1962260 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 368 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 163 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 531 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55554 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 55554 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20216 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 20216 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 75495 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 75495 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 55758 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 55758 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97640 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 97640 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 368 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 163 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 55758 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 173135 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 229424 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 368 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 163 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 55758 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 173135 # number of overall misses
system.cpu0.l2cache.overall_misses::total 229424 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 12005000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4151000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 16156000 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 182701500 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 182701500 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 44056000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 44056000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 567499 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 567499 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3992148999 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 3992148999 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3821727998 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3821727998 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3406655997 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3406655997 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 12005000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4151000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3821727998 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 7398804996 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 11236688994 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 12005000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4151000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3821727998 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 7398804996 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 11236688994 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 61263 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14873 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 76136 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 504685 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 504685 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 1522610 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 1522610 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55554 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 55554 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20216 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20216 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280798 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 280798 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1310553 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 1310553 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 524197 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 524197 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 61263 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14873 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1310553 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 804995 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2191684 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 61263 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14873 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1310553 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 804995 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2191684 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.006007 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010959 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.006974 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.268859 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.268859 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042545 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042545 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186266 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186266 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.006007 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010959 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042545 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.215076 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.104679 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.006007 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010959 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042545 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.215076 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.104679 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32622.282609 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25466.257669 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30425.612053 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3288.719084 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3288.719084 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2179.263949 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2179.263949 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 567499 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 567499 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 52879.647646 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 52879.647646 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 68541.339324 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68541.339324 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34889.963099 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34889.963099 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32622.282609 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25466.257669 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68541.339324 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42734.311352 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 48977.827054 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32622.282609 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25466.257669 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68541.339324 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42734.311352 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 48977.827054 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 25.750000 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 233354 # number of writebacks
system.cpu0.l2cache.writebacks::total 233354 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 32795 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 32795 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 40 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 40 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 826 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 826 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 40 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33621 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 33662 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 40 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33621 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 33662 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 368 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 162 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 530 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259813 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 259813 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55554 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55554 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20216 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20216 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42700 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 42700 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 55718 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 55718 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 96814 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 96814 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 368 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 162 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 55718 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 139514 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 195762 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 368 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 162 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 55718 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 139514 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259813 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 455575 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31833 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34837 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60326 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63330 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9797000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3166000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 12963000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21619436690 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21619436690 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1442424499 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1442424499 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 361912494 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 361912494 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 489499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 489499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2411987500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2411987500 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3485757498 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3485757498 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2763293997 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2763293997 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9797000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3166000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3485757498 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5175281497 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 8674001995 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9797000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3166000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3485757498 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5175281497 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21619436690 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 30293438685 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398120500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6372996000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6771116500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5179186462 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5179186462 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398120500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11552182462 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11950302962 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.006007 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010892 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.006961 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.152067 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.152067 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042515 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042515 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184690 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184690 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.006007 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010892 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042515 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173310 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.089320 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.006007 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010892 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042515 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173310 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207865 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24458.490566 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83211.527868 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83211.527868 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25964.367984 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25964.367984 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17902.280075 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17902.280075 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 489499 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 489499 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56486.826698 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56486.826698 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62560.707455 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62560.707455 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28542.297571 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28542.297571 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62560.707455 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37095.069291 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44308.915903 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62560.707455 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37095.069291 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83211.527868 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66494.954036 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.923570 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194365.660074 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181770.486154 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181770.486154 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191495.913238 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188698.925659 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests 4273775 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2158237 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 328951 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324011 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq 121086 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 2004866 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28493 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28493 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 738565 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 1555705 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 211042 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 317280 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 85893 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42559 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 113529 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 299037 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 295734 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1310580 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595787 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 3352 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3937175 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2734284 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32274 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130084 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 6833817 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167765632 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103829284 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59492 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 245052 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 271899460 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 1019958 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 3249040 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.119755 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.329325 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 2864891 88.18% 88.18% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 379209 11.67% 99.85% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 4940 0.15% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 3249040 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 4275333939 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 114905569 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 1969437864 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1292879675 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 17411978 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 68871898 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 4004674 # Number of BP lookups
system.cpu1.branchPred.condPredicted 2314065 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 245791 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 2020541 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 1485653 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 73.527486 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 787487 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 5760 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 15918 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 15918 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8430 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3084 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 4404 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 11514 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 608.824040 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 3343.959858 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 10992 95.47% 95.47% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191 174 1.51% 96.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287 180 1.56% 98.54% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383 59 0.51% 99.05% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.17% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.20% 99.37% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.04% 99.41% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767 43 0.37% 99.78% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.04% 99.83% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 19 0.17% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 11514 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 3241 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11888.614625 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10569.570735 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 6910.032291 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383 2741 84.57% 84.57% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767 457 14.10% 98.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.08% 99.75% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535 7 0.22% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 3241 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 79820713468 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.176976 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.384068 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 65723853356 82.34% 82.34% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 14081443112 17.64% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2 10527000 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3 1956000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4 949000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5 421000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6 996500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7 109000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8 31000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9 149000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10 36500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11 15000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12 23000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13 37500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15 151500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 79820713468 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1248 73.11% 73.11% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 459 26.89% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 1707 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15918 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15918 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1707 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1707 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 17625 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 3542440 # DTB read hits
system.cpu1.dtb.read_misses 14035 # DTB read misses
system.cpu1.dtb.write_hits 3032103 # DTB write hits
system.cpu1.dtb.write_misses 1883 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1668 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 364 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 3556475 # DTB read accesses
system.cpu1.dtb.write_accesses 3033986 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 6574543 # DTB hits
system.cpu1.dtb.misses 15918 # DTB misses
system.cpu1.dtb.accesses 6590461 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 6720 # Table walker walks requested
system.cpu1.itb.walker.walksShort 6720 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4032 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2330 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 358 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 6362 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 276.642565 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 2156.603073 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-4095 6226 97.86% 97.86% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-8191 61 0.96% 98.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-12287 38 0.60% 99.42% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-16383 9 0.14% 99.56% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-20479 2 0.03% 99.59% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-24575 2 0.03% 99.62% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-28671 16 0.25% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-32767 7 0.11% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::40960-45055 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 6362 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1209 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11358.974359 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10416.514513 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5795.722698 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191 235 19.44% 19.44% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383 915 75.68% 95.12% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575 19 1.57% 96.69% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767 26 2.15% 98.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959 6 0.50% 99.34% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.33% 99.67% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.08% 99.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.08% 99.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::73728-81919 2 0.17% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1209 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 15394402028 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.620378 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.485344 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 5844439264 37.96% 37.96% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 9549582764 62.03% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 380000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 15394402028 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 707 83.08% 83.08% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 144 16.92% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 851 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6720 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6720 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 851 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 851 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 7571 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 7202560 # ITB inst hits
system.cpu1.itb.inst_misses 6720 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 915 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 341 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 7209280 # ITB inst accesses
system.cpu1.itb.hits 7202560 # DTB hits
system.cpu1.itb.misses 6720 # DTB misses
system.cpu1.itb.accesses 7209280 # DTB accesses
system.cpu1.numCycles 32401432 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 8088351 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 21358444 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 4004674 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 2273140 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 22559668 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 709698 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 89320 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 30191 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 187953 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 272100 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 17466 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 7201931 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 106041 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2579 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 31599898 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.827450 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.197285 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 19506083 61.73% 61.73% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 4380023 13.86% 75.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 1374078 4.35% 79.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 6339714 20.06% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 31599898 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.123596 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.659182 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 6634182 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 16202869 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 7616699 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 910855 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 235293 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 619161 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 122169 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 20057728 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 931915 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 235293 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 7874159 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2260152 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 11399374 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 7269011 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 2561909 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 19031053 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 153065 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 202989 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 28113 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 12734 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1710748 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 18778237 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 89017572 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 21965763 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 3 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 16813455 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1964782 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 364894 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 300103 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 2457661 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 3778976 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 3342332 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 554105 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 450807 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 18329749 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 508607 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 18175118 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 83980 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 1786298 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 4127648 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 40965 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 31599898 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.575164 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.924804 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 20823460 65.90% 65.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 5404189 17.10% 83.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 3573075 11.31% 94.31% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 1571925 4.97% 99.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 227241 0.72% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 31599898 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 1136230 27.62% 27.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 665 0.02% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1332872 32.40% 60.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 1643603 39.96% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 11198655 61.62% 61.62% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 26151 0.14% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.76% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 3134 0.02% 61.78% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 3723841 20.49% 82.27% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 3223313 17.73% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 18175118 # Type of FU issued
system.cpu1.iq.rate 0.560936 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4113370 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.226319 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 72147484 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 20632628 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 17784107 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 22288464 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 72358 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 345916 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 595 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 8007 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 274863 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 35609 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 53341 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 235293 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 517337 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 146372 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 18855001 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 3778976 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 3342332 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 266125 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 6620 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 133975 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 8007 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 29726 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 104216 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 133942 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 17973018 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 3647924 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 186185 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 16645 # number of nop insts executed
system.cpu1.iew.exec_refs 6817035 # number of memory reference insts executed
system.cpu1.iew.exec_branches 2587014 # Number of branches executed
system.cpu1.iew.exec_stores 3169111 # Number of stores executed
system.cpu1.iew.exec_rate 0.554698 # Inst execution rate
system.cpu1.iew.wb_sent 17871186 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 17784107 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 8844810 # num instructions producing a value
system.cpu1.iew.wb_consumers 13737258 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.548868 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.643856 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 1617174 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 467642 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 126235 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 31232048 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.546078 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.299760 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 22985371 73.60% 73.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 4918403 15.75% 89.34% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1437568 4.60% 93.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 538908 1.73% 95.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 452299 1.45% 97.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 299028 0.96% 98.08% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 181643 0.58% 98.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 99960 0.32% 98.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 318868 1.02% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 31232048 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 13919439 # Number of instructions committed
system.cpu1.commit.committedOps 17055121 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 6500529 # Number of memory references committed
system.cpu1.commit.loads 3433060 # Number of loads committed
system.cpu1.commit.membars 191637 # Number of memory barriers committed
system.cpu1.commit.branches 2464934 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 15221061 # Number of committed integer instructions.
system.cpu1.commit.function_calls 413171 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 10526100 61.72% 61.72% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 25358 0.15% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.87% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 3134 0.02% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 3433060 20.13% 82.01% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 3067469 17.99% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 17055121 # Class of committed instruction
system.cpu1.commit.bw_lim_events 318868 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 48693377 # The number of ROB reads
system.cpu1.rob.rob_writes 37704462 # The number of ROB writes
system.cpu1.timesIdled 54449 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 801534 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5641978926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 13916375 # Number of Instructions Simulated
system.cpu1.committedOps 17052057 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.328295 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.328295 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.429499 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.429499 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 20171144 # number of integer regfile reads
system.cpu1.int_regfile_writes 11610273 # number of integer regfile writes
system.cpu1.cc_regfile_reads 64505089 # number of cc regfile reads
system.cpu1.cc_regfile_writes 5511942 # number of cc regfile writes
system.cpu1.misc_regfile_reads 46426595 # number of misc regfile reads
system.cpu1.misc_regfile_writes 345736 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 150581 # number of replacements
system.cpu1.dcache.tags.tagsinuse 478.131368 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 5834465 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 150940 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 38.654200 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 89605225500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.131368 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.933850 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.933850 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 12862288 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 12862288 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 3070880 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 3070880 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 2527415 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 2527415 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42897 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 42897 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70538 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 70538 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61948 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 61948 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 5598295 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 5598295 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 5641192 # number of overall hits
system.cpu1.dcache.overall_hits::total 5641192 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 179007 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 179007 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 316590 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 316590 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23941 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 23941 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17385 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 17385 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23392 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23392 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 495597 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 495597 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 519538 # number of overall misses
system.cpu1.dcache.overall_misses::total 519538 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3308418500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3308418500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11036821442 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 11036821442 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 357595000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 357595000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 636551500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 636551500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 787500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 787500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 14345239942 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 14345239942 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 14345239942 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 14345239942 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 3249887 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 3249887 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 2844005 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 2844005 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66838 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 66838 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87923 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 87923 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85340 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 85340 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 6093892 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 6093892 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 6160730 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 6160730 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055081 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.055081 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111318 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.111318 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358194 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358194 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.197730 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.197730 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274104 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274104 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081327 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.081327 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084331 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.084331 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18482.062154 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 18482.062154 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34861.560510 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34861.560510 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20569.168824 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20569.168824 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27212.358926 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27212.358926 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28945.372837 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 28945.372837 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27611.531672 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 27611.531672 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 640 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1636825 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 30227 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 23.703704 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 54.151090 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 150582 # number of writebacks
system.cpu1.dcache.writebacks::total 150582 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62660 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 62660 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 238202 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 238202 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12477 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12477 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 300862 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 300862 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 300862 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 300862 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116347 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 116347 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78388 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 78388 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23063 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 23063 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4908 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4908 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23392 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23392 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 194735 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 194735 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 217798 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 217798 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3053 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3053 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5464 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5464 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1737573500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1737573500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2770904951 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2770904951 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 402982000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 402982000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95410500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95410500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 613166500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 613166500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 780500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 780500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4508478451 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4508478451 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4911460451 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4911460451 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 434201000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 434201000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 300720500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 300720500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 734921500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 734921500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035800 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027563 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027563 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.345058 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.345058 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055822 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055822 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274104 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274104 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031956 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.031956 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035353 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.035353 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14934.407419 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14934.407419 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35348.585893 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35348.585893 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17473.095434 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17473.095434 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19439.792176 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19439.792176 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26212.658174 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26212.658174 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23151.865104 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23151.865104 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22550.530542 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22550.530542 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142221.094006 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142221.094006 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124728.535877 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124728.535877 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134502.470717 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134502.470717 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 558748 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.431934 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 6622904 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 559260 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 11.842263 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 79422943000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.431934 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975453 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975453 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 14962745 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 14962745 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 6622904 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 6622904 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 6622904 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 6622904 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 6622904 # number of overall hits
system.cpu1.icache.overall_hits::total 6622904 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 578838 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 578838 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 578838 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 578838 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 578838 # number of overall misses
system.cpu1.icache.overall_misses::total 578838 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5256613547 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5256613547 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5256613547 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5256613547 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5256613547 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5256613547 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 7201742 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 7201742 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 7201742 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 7201742 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 7201742 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 7201742 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.080375 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.080375 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.080375 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.080375 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.080375 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.080375 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9081.320762 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9081.320762 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9081.320762 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9081.320762 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9081.320762 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9081.320762 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 509077 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 85 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 41733 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.198428 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 85 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.writebacks::writebacks 558748 # number of writebacks
system.cpu1.icache.writebacks::total 558748 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19577 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 19577 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 19577 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 19577 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 19577 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 19577 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 559261 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 559261 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 559261 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 559261 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 559261 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 559261 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4811835313 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4811835313 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4811835313 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 4811835313 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4811835313 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 4811835313 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13519000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13519000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13519000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 13519000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077656 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077656 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077656 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.077656 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077656 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.077656 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8603.917157 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8603.917157 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8603.917157 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8603.917157 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8603.917157 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8603.917157 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132539.215686 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132539.215686 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132539.215686 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132539.215686 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 109637 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 110252 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 555 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 50212 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 32977 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15133.378698 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1241042 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 48162 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 25.768074 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14693.794117 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.871324 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.967669 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 426.745588 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.896838 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000602 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026046 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.923668 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 969 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14157 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 644 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 315 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2756 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10644 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059143 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864075 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 24496056 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 24496056 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 12197 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7113 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 19310 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 93036 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 93036 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 603907 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 603907 # number of WritebackClean hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 17416 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 17416 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 548751 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 548751 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 79273 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 79273 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 12197 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7113 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 548751 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 96689 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 664750 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 12197 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7113 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 548751 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 96689 # number of overall hits
system.cpu1.l2cache.overall_hits::total 664750 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 440 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 294 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 734 # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29045 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 29045 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23391 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 23391 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32566 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 32566 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 10510 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 10510 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 65040 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 65040 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 440 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 294 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 10510 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 97606 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 108850 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 440 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 294 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 10510 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 97606 # number of overall misses
system.cpu1.l2cache.overall_misses::total 108850 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9330000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5916500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 15246500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64398500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 64398500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 62315000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 62315000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 770000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 770000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1749045497 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1749045497 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 618682999 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 618682999 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1487002498 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1487002498 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9330000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5916500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 618682999 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3236047995 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 3869977494 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9330000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5916500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 618682999 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3236047995 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 3869977494 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12637 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7407 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 20044 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 93037 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 93037 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 603907 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 603907 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29045 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 29045 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23392 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23392 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 49982 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 49982 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 559261 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 559261 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 144313 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 144313 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12637 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7407 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 559261 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 194295 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 773600 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12637 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7407 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 559261 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 194295 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 773600 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034818 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.039692 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.036619 # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000011 # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000011 # miss rate for WritebackDirty accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999957 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999957 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.651555 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.651555 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018793 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018793 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.450687 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.450687 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034818 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.039692 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018793 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.502360 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.140706 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034818 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.039692 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018793 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.502360 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.140706 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21204.545455 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20124.149660 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20771.798365 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2217.197452 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2217.197452 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2664.058826 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2664.058826 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53707.716545 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53707.716545 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 58866.127402 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 58866.127402 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22862.892036 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22862.892036 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21204.545455 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20124.149660 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 58866.127402 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33154.191289 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 35553.307249 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21204.545455 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20124.149660 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 58866.127402 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33154.191289 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 35553.307249 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 261 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 26427 # number of writebacks
system.cpu1.l2cache.writebacks::total 26427 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 17 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1048 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 1048 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 32 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 17 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1080 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 1099 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 17 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1080 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 1099 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 439 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 277 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 716 # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19656 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 19656 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29045 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29045 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23391 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23391 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31518 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 31518 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10509 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10509 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 65008 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 65008 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 439 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 277 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10509 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96526 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 107751 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 439 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 277 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10509 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96526 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19656 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 127407 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3053 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3155 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5464 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5566 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6677500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4041000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10718500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1141457953 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1141457953 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 589371500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 589371500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 437078999 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 437078999 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 728000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 728000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1480447500 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1480447500 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 555611499 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 555611499 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1095693498 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1095693498 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6677500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4041000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 555611499 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2576140998 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 3142470997 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6677500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4041000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 555611499 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2576140998 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1141457953 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 4283928950 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12754000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 409480000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 422234000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 282396995 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 282396995 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12754000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 691876995 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 704630995 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.034739 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037397 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.035721 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000011 # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000011 # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.630587 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.630587 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018791 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018791 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.450465 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.450465 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.034739 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037397 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018791 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.496801 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139285 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.034739 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037397 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018791 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.496801 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.164694 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14969.972067 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58071.731431 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58071.731431 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20291.668101 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20291.668101 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18685.776538 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18685.776538 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46971.492480 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46971.492480 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 52870.063660 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 52870.063660 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16854.748616 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16854.748616 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 52870.063660 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26688.570934 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29164.193344 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 52870.063660 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26688.570934 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58071.731431 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33623.968463 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125039.215686 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134123.812643 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133830.110935 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117128.575280 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117128.575280 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125039.215686 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126624.633053 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126595.579411 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests 1522873 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 769340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12387 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 172724 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169892 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2832 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq 26445 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 767980 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2411 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2411 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 120637 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 616293 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 90499 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 23834 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 71062 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41585 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 84984 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 57226 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 54414 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 559261 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 224052 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1677474 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 729934 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16099 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27235 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2450742 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 71554208 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24804884 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29628 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50548 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 96439268 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 367369 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1124026 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.173917 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.385628 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 931371 82.86% 82.86% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 189823 16.89% 99.75% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 2832 0.25% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1124026 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 1482640983 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 79919843 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 839140704 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 323172006 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 8701980 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 14614966 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31018 # Transaction distribution
system.iobus.trans_dist::ReadResp 31018 # Transaction distribution
system.iobus.trans_dist::WriteReq 59424 # Transaction distribution
system.iobus.trans_dist::WriteResp 59424 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40406500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 111000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 580500 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6147500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 34101000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 187141705 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36458 # number of replacements
system.iocache.tags.tagsinuse 14.554769 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 256290748000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.554769 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.909673 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.909673 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 32655877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 32655877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4577690828 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4577690828 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 32655877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 32655877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 32655877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 32655877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129586.813492 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129586.813492 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126371.765349 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126371.765349 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 129586.813492 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 129586.813492 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 129586.813492 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 129586.813492 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 20055877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 20055877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764790800 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2764790800 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 20055877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 20055877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 20055877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 20055877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79586.813492 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 79586.813492 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76324.834364 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76324.834364 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 79586.813492 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 79586.813492 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 79586.813492 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 79586.813492 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 124479 # number of replacements
system.l2c.tags.tagsinuse 63294.400008 # Cycle average of tags in use
system.l2c.tags.total_refs 441070 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 188520 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.339646 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 13356.956010 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.526803 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 2.143514 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 8260.020738 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2811.874260 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35051.751724 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.709100 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909838 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1633.190711 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 526.401033 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1632.916278 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.203811 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000237 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000033 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.126038 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.042906 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.534847 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.024921 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.008032 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.024916 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.965796 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 30816 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 33209 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 147 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 5952 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 24713 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 581 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4379 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 28217 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.470215 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.506729 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6015523 # Number of tag accesses
system.l2c.tags.data_accesses 6015523 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 259782 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 259782 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 32612 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1902 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 34514 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2095 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 1014 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 3109 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 4349 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1510 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5859 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 224 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 137 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 36140 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 48981 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48009 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 43 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 16 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 7839 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 5530 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 2822 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 149741 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 224 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 137 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 36140 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 53330 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 48009 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 43 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 16 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 7839 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 7040 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 2822 # number of demand (read+write) hits
system.l2c.demand_hits::total 155600 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 224 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 137 # number of overall hits
system.l2c.overall_hits::cpu0.inst 36140 # number of overall hits
system.l2c.overall_hits::cpu0.data 53330 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 48009 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 43 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 16 # number of overall hits
system.l2c.overall_hits::cpu1.inst 7839 # number of overall hits
system.l2c.overall_hits::cpu1.data 7040 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 2822 # number of overall hits
system.l2c.overall_hits::total 155600 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 9744 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 2432 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 12176 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 852 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1310 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2162 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 10997 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 7998 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 18995 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 19577 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 9060 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132167 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 2670 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 969 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5888 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 170365 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 19577 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 20057 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 132167 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2670 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 8967 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 5888 # number of demand (read+write) misses
system.l2c.demand_misses::total 189360 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 19577 # number of overall misses
system.l2c.overall_misses::cpu0.data 20057 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 132167 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2670 # number of overall misses
system.l2c.overall_misses::cpu1.data 8967 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 5888 # number of overall misses
system.l2c.overall_misses::total 189360 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 27825000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 4797500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 32622500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4443000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3758500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 8201500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1661698000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1063904000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2725602000 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 3708000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 388000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2601291001 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 1255659000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20759731468 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 400000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 133000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 357760500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 136813000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1070589447 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 26186473416 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 3708000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 388000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 2601291001 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 2917357000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20759731468 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 400000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 133000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 357760500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1200717000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1070589447 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 28912075416 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 3708000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 388000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 2601291001 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 2917357000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20759731468 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 400000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 133000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 357760500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1200717000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1070589447 # number of overall miss cycles
system.l2c.overall_miss_latency::total 28912075416 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 259782 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 259782 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 42356 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4334 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 46690 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 2947 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 2324 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 5271 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 15346 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 9508 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 24854 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 251 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 140 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 55717 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 58041 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180176 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 46 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 17 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 10509 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 6499 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8710 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 320106 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 251 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 140 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 55717 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 73387 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180176 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 46 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 17 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 10509 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 16007 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8710 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 344960 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 251 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 140 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 55717 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 73387 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180176 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 46 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 17 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 10509 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 16007 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8710 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 344960 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.230050 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.561144 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.260784 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.289108 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.563683 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.410169 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.716604 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.841186 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.764263 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.107570 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.021429 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.351365 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.156097 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.733544 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.065217 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.058824 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.254068 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.149100 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.676005 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.532214 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.107570 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.021429 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.351365 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.273305 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.733544 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.065217 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.058824 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.254068 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.560192 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.676005 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.548933 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.107570 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.021429 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.351365 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.273305 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.733544 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.065217 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.058824 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.254068 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.560192 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.676005 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.548933 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2855.603448 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1972.656250 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 2679.246058 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5214.788732 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2869.083969 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 3793.478261 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151104.664909 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133021.255314 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 143490.497499 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137333.333333 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132874.853195 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138593.708609 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157071.973095 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 133333.333333 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 133000 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133992.696629 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141189.886481 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181825.653363 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 153708.058674 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137333.333333 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 132874.853195 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 145453.308072 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157071.973095 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 133333.333333 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 133992.696629 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 133903.981265 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181825.653363 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 152683.119011 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137333.333333 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 132874.853195 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 145453.308072 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157071.973095 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 133333.333333 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 133992.696629 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 133903.981265 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181825.653363 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 152683.119011 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 97745 # number of writebacks
system.l2c.writebacks::total 97745 # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 16 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 18 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 3037 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 3037 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 9744 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 2432 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 12176 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 852 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1310 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2162 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 10997 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 7998 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 18995 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19575 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9060 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132167 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2654 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 969 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5888 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 170347 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 19575 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 20057 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132167 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2654 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 8967 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5888 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 189342 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 19575 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 20057 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132167 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2654 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 8967 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5888 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 189342 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31833 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3050 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 37989 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 30904 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60326 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5461 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 68893 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 709212999 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 175914500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 885127499 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 63641994 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 96652999 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 160294993 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1551726006 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 983917017 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 2535643023 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3438000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 358000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2405309042 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1165053013 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19438018096 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 370000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 329498524 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 127120506 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1011699481 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 24480987662 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3438000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 358000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 2405309042 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2716779019 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19438018096 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 370000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 123000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 329498524 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1111037523 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1011699481 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 27016630685 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3438000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 358000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 2405309042 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2716779019 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19438018096 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 370000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 123000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 329498524 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1111037523 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1011699481 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 27016630685 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344048000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5799985504 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 354512005 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6509462509 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4694674541 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 241390508 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4936065049 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344048000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10494660045 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10917000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 595902513 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 11445527558 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.230050 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.561144 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.260784 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.289108 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563683 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.410169 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.716604 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.841186 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.764263 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.107570 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.021429 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.351329 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.156097 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733544 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.065217 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.058824 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.252545 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.149100 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.676005 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.532158 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.107570 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021429 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.351329 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.273305 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733544 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.065217 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.058824 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.252545 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.560192 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.676005 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.548881 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.107570 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021429 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.351329 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.273305 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733544 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.065217 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.058824 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.252545 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.560192 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.676005 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.548881 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72784.585283 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72333.264803 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72694.439800 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74697.176056 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73780.915267 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74141.994912 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141104.483586 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123020.382221 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 133490.024901 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122876.579413 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128593.047792 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124151.666918 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131187.312693 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143712.467270 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122876.579413 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135452.910156 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124151.666918 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123902.924389 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 142686.940483 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122876.579413 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135452.910156 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124151.666918 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123902.924389 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 142686.940483 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.405366 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107029.411765 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116233.444262 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171351.246650 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164765.891307 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100120.492742 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159722.529414 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173965.786643 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107029.411765 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109119.669108 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 166134.840376 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 37989 # Transaction distribution
system.membus.trans_dist::ReadResp 208587 # Transaction distribution
system.membus.trans_dist::WriteReq 30904 # Transaction distribution
system.membus.trans_dist::WriteResp 30904 # Transaction distribution
system.membus.trans_dist::WritebackDirty 133951 # Transaction distribution
system.membus.trans_dist::CleanEvict 15326 # Transaction distribution
system.membus.trans_dist::UpgradeReq 74253 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 40479 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 38529 # Transaction distribution
system.membus.trans_dist::ReadExResp 18901 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 170599 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13702 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641454 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 763128 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 836077 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27404 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18415544 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18606080 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 20924224 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 120501 # Total snoops (count)
system.membus.snoop_fanout::samples 578275 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 578275 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 578275 # Request fanout histogram
system.membus.reqLayer0.occupancy 81956500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 11341491 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 978727928 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1093472967 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1338381 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests 990338 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 533884 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 147185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 20219 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 19375 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 844 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 37992 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 475955 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 393750 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 117353 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 108673 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 43588 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 152261 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 50171 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 50171 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 437979 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1264500 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 260756 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1525256 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35008152 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3970344 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 38978496 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 440946 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 906523 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.342627 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.476546 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 596768 65.83% 65.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 308911 34.08% 99.91% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 844 0.09% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 906523 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 872587716 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 657818310 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 206175111 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1860 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2731 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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