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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Steve Reinhardt f5d1dd75e5 stats: overdue updates to long regressions
2016-03-16 13:03:49 -07:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.832923 # Number of seconds simulated
sim_ticks 2832922792000 # Number of ticks simulated
final_tick 2832922792000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 64859 # Simulator instruction rate (inst/s)
host_op_rate 78668 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1624421261 # Simulator tick rate (ticks/s)
host_mem_usage 564480 # Number of bytes of host memory used
host_seconds 1743.96 # Real time elapsed on the host
sim_insts 113110851 # Number of instructions simulated
sim_ops 137193114 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1316352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 10702440 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1316352 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1316352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7997632 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::total 8015156 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22815 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 169993 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 124963 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::total 129344 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 497 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 464662 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3312200 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3777879 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 464662 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 464662 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2823103 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2829289 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2823103 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 497 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 464662 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3318386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6607168 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 169994 # Number of read requests accepted
system.physmem.writeReqs 129344 # Number of write requests accepted
system.physmem.readBursts 169994 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 129344 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10868544 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue
system.physmem.bytesWritten 8027328 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10702504 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8015156 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11395 # Per bank write bursts
system.physmem.perBankRdBursts::1 10614 # Per bank write bursts
system.physmem.perBankRdBursts::2 11056 # Per bank write bursts
system.physmem.perBankRdBursts::3 11362 # Per bank write bursts
system.physmem.perBankRdBursts::4 12761 # Per bank write bursts
system.physmem.perBankRdBursts::5 10093 # Per bank write bursts
system.physmem.perBankRdBursts::6 10906 # Per bank write bursts
system.physmem.perBankRdBursts::7 11082 # Per bank write bursts
system.physmem.perBankRdBursts::8 10555 # Per bank write bursts
system.physmem.perBankRdBursts::9 10525 # Per bank write bursts
system.physmem.perBankRdBursts::10 10031 # Per bank write bursts
system.physmem.perBankRdBursts::11 8841 # Per bank write bursts
system.physmem.perBankRdBursts::12 9976 # Per bank write bursts
system.physmem.perBankRdBursts::13 10659 # Per bank write bursts
system.physmem.perBankRdBursts::14 9879 # Per bank write bursts
system.physmem.perBankRdBursts::15 10086 # Per bank write bursts
system.physmem.perBankWrBursts::0 8598 # Per bank write bursts
system.physmem.perBankWrBursts::1 7964 # Per bank write bursts
system.physmem.perBankWrBursts::2 8488 # Per bank write bursts
system.physmem.perBankWrBursts::3 8679 # Per bank write bursts
system.physmem.perBankWrBursts::4 7544 # Per bank write bursts
system.physmem.perBankWrBursts::5 7468 # Per bank write bursts
system.physmem.perBankWrBursts::6 8076 # Per bank write bursts
system.physmem.perBankWrBursts::7 8176 # Per bank write bursts
system.physmem.perBankWrBursts::8 8056 # Per bank write bursts
system.physmem.perBankWrBursts::9 7912 # Per bank write bursts
system.physmem.perBankWrBursts::10 7497 # Per bank write bursts
system.physmem.perBankWrBursts::11 6567 # Per bank write bursts
system.physmem.perBankWrBursts::12 7556 # Per bank write bursts
system.physmem.perBankWrBursts::13 8041 # Per bank write bursts
system.physmem.perBankWrBursts::14 7358 # Per bank write bursts
system.physmem.perBankWrBursts::15 7447 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
system.physmem.totGap 2832922560000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 166442 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 124963 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 150475 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 16443 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2160 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 726 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1876 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2935 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6553 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6085 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6552 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6402 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6670 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8576 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7511 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7522 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1227 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 325 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 226 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 78 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 70 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62162 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 303.976835 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 179.556802 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 324.609366 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 23353 37.57% 37.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 15037 24.19% 61.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6420 10.33% 72.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3598 5.79% 77.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2572 4.14% 82.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1554 2.50% 84.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1555 2.50% 87.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1056 1.70% 88.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7017 11.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62162 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6134 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 27.682426 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 569.995454 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6133 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6134 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6134 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.447832 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.494220 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 14.258033 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5448 88.82% 88.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 109 1.78% 90.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 26 0.42% 91.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 55 0.90% 91.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 22 0.36% 92.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 18 0.29% 92.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 54 0.88% 93.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 11 0.18% 93.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 137 2.23% 95.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 15 0.24% 96.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 11 0.18% 96.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 9 0.15% 96.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 67 1.09% 97.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 4 0.07% 97.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 9 0.15% 97.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 29 0.47% 98.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 82 1.34% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.02% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 7 0.11% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 5 0.08% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 3 0.05% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6134 # Writes before turning the bus around for reads
system.physmem.totQLat 2139801000 # Total ticks spent queuing
system.physmem.totMemAccLat 5323944750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 849105000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12600.33 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 31350.33 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.97 # Average write queue length when enqueuing
system.physmem.readRowHits 139332 # Number of row buffer hits during reads
system.physmem.writeRowHits 93753 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.73 # Row buffer hit rate for writes
system.physmem.avgGap 9463959.00 # Average gap between requests
system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 247869720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 135246375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 696290400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 421154640 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 83656164285 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1626368380500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1896557542080 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.471316 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2705472781500 # Time in different power states
system.physmem_0.memoryStateTime::REF 94597360000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 32852637000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 628305600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 391612320 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 81913765770 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1627896800250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1896206166975 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.347283 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2708023579500 # Time in different power states
system.physmem_1.memoryStateTime::REF 94597360000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 30297375500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu.branchPred.lookups 46900870 # Number of BP lookups
system.cpu.branchPred.condPredicted 24033937 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1233884 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 29535620 # Number of BTB lookups
system.cpu.branchPred.BTBHits 21344859 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 72.268193 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 11734674 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 33890 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.walker.walks 9704 # Table walker walks requested
system.cpu.checker.dtb.walker.walksShort 9704 # Table walker walks initiated with short descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 9704 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 9704 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 9704 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walkPageSizes::4K 6218 82.47% 82.47% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::1M 1322 17.53% 100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total 7540 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9704 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9704 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7540 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7540 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 17244 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 24578942 # DTB read hits
system.cpu.checker.dtb.read_misses 8287 # DTB read misses
system.cpu.checker.dtb.write_hits 19634178 # DTB write hits
system.cpu.checker.dtb.write_misses 1417 # DTB write misses
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 1642 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 24587229 # DTB read accesses
system.cpu.checker.dtb.write_accesses 19635595 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dtb.hits 44213120 # DTB hits
system.cpu.checker.dtb.misses 9704 # DTB misses
system.cpu.checker.dtb.accesses 44222824 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested
system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 4825 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 375090000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.26% 88.26% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::1M 372 11.74% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 3170 # Table walker page sizes translated
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4825 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4825 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.inst_hits 115809550 # ITB inst hits
system.cpu.checker.itb.inst_misses 4825 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 2976 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
system.cpu.checker.itb.inst_accesses 115814375 # ITB inst accesses
system.cpu.checker.itb.hits 115809550 # DTB hits
system.cpu.checker.itb.misses 4825 # DTB misses
system.cpu.checker.itb.accesses 115814375 # DTB accesses
system.cpu.checker.numCycles 139043856 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 71837 # Table walker walks requested
system.cpu.dtb.walker.walksShort 71837 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29758 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22348 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 19731 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 52106 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 420.441024 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 2560.543879 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-4095 50336 96.60% 96.60% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::4096-8191 584 1.12% 97.72% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-12287 523 1.00% 98.73% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::12288-16383 337 0.65% 99.37% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-20479 50 0.10% 99.47% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.42% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-28671 15 0.03% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 52106 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 17457 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 11531.334135 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 9171.811391 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 8140.859549 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767 17274 98.95% 98.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 17457 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 131387254816 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.617449 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.493362 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 131332759316 99.96% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 37388500 0.03% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 6986000 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 6081500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 1205000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 646500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 1379500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 798500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 131387254816 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6345 82.34% 82.34% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1361 17.66% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7706 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71837 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71837 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7706 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7706 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 79543 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 25453240 # DTB read hits
system.cpu.dtb.read_misses 61907 # DTB read misses
system.cpu.dtb.write_hits 19910032 # DTB write hits
system.cpu.dtb.write_misses 9930 # DTB write misses
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 357 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1331 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 25515147 # DTB read accesses
system.cpu.dtb.write_accesses 19919962 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 45363272 # DTB hits
system.cpu.dtb.misses 71837 # DTB misses
system.cpu.dtb.accesses 45435109 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 13224 # Table walker walks requested
system.cpu.itb.walker.walksShort 13224 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2 7779 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 1510 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 11714 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 663.436913 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 2983.675240 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-4095 11112 94.86% 94.86% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::4096-8191 167 1.43% 96.29% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 97.93% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::12288-16383 98 0.84% 98.76% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-20479 101 0.86% 99.62% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::20480-24575 31 0.26% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 11714 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 4832 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 11551.427980 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 9033.563647 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 8305.140651 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383 3848 79.64% 79.64% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767 915 18.94% 98.57% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-49151 67 1.39% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 4832 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 24013010416 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.681227 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.466165 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 7656484500 31.88% 31.88% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 16354802916 68.11% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 1665500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 24013010416 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 3004 90.43% 90.43% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 318 9.57% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 13224 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 13224 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 16546 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 66215474 # ITB inst hits
system.cpu.itb.inst_misses 13224 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 3093 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 2222 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 66228698 # ITB inst accesses
system.cpu.itb.hits 66215474 # DTB hits
system.cpu.itb.misses 13224 # DTB misses
system.cpu.itb.accesses 66228698 # DTB accesses
system.cpu.numCycles 278849039 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 104825039 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 184547548 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46900870 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33079533 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 161783291 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6174948 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 189837 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 10053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 357428 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 560111 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 66214357 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1060583 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 6520 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 270813408 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.831546 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.217852 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 171553183 63.35% 63.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29255757 10.80% 74.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14075334 5.20% 79.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55929134 20.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 270813408 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.168194 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.661819 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 77914241 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 121818980 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64632452 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3838198 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2609537 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3423128 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 486335 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 157406934 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3698656 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2609537 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83756930 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 11780773 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 76597873 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62631659 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 33436636 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146755972 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 956855 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 452398 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 63697 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 16353 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 30702971 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150428298 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 678515900 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 164385434 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 141750240 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 8678055 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2842275 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2646130 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13851175 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26402053 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 21296304 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1688639 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2128632 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143481450 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2121615 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143268725 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 270645 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8409947 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14700028 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 125764 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 270813408 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.529031 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.865143 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 182463558 67.38% 67.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45313359 16.73% 84.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31963465 11.80% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10263701 3.79% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 809292 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 270813408 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 7332102 32.71% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5631471 25.13% 57.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9448597 42.16% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 95958706 66.98% 66.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 113835 0.08% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26183625 18.28% 85.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21001646 14.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 143268725 # Type of FU issued
system.cpu.iq.rate 0.513786 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22412202 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156435 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 579998115 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 154018366 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 140157777 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35590 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 165655240 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23350 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 322841 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1496212 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 510 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18521 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 704329 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 88213 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6464 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 2609537 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1244131 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 534453 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 145804019 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 26402053 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 21296304 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17993 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 500261 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18521 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 317950 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471174 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 789124 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 142326073 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25781011 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 870919 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 200954 # number of nop insts executed
system.cpu.iew.exec_refs 46653702 # number of memory reference insts executed
system.cpu.iew.exec_branches 26511824 # Number of branches executed
system.cpu.iew.exec_stores 20872691 # Number of stores executed
system.cpu.iew.exec_rate 0.510405 # Inst execution rate
system.cpu.iew.wb_sent 141939572 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 140169144 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63244057 # num instructions producing a value
system.cpu.iew.wb_consumers 95727511 # num instructions consuming a value
system.cpu.iew.wb_rate 0.502670 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660668 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7609153 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995851 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 755947 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 267866819 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.512747 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.116675 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 194366787 72.56% 72.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43325916 16.17% 88.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15476786 5.78% 94.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4394475 1.64% 96.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6423634 2.40% 98.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1609805 0.60% 99.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 801244 0.30% 99.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 411295 0.15% 99.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1056877 0.39% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 267866819 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113265756 # Number of instructions committed
system.cpu.commit.committedOps 137348019 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 45497816 # Number of memory references committed
system.cpu.commit.loads 24905841 # Number of loads committed
system.cpu.commit.membars 814912 # Number of memory barriers committed
system.cpu.commit.branches 26026635 # Number of branches committed
system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
system.cpu.commit.int_insts 120174652 # Number of committed integer instructions.
system.cpu.commit.function_calls 4885050 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 91728853 66.79% 66.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 112775 0.08% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 24905841 18.13% 85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20591975 14.99% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 137348019 # Class of committed instruction
system.cpu.commit.bw_lim_events 1056877 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389577087 # The number of ROB reads
system.cpu.rob.rob_writes 292847921 # The number of ROB writes
system.cpu.timesIdled 893517 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8035631 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5386996546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113110851 # Number of Instructions Simulated
system.cpu.committedOps 137193114 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.465272 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.465272 # CPI: Total CPI of All Threads
system.cpu.ipc 0.405635 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.405635 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 155766897 # number of integer regfile reads
system.cpu.int_regfile_writes 88591583 # number of integer regfile writes
system.cpu.fp_regfile_reads 9527 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
system.cpu.cc_regfile_reads 502787810 # number of cc regfile reads
system.cpu.cc_regfile_writes 53167573 # number of cc regfile writes
system.cpu.misc_regfile_reads 348401646 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521641 # number of misc regfile writes
system.cpu.dcache.tags.replacements 837383 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.925650 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40103246 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 837895 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.861899 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.925650 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 179305026 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179305026 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23303846 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23303846 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15548555 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15548555 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 345967 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345967 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441680 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441680 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460325 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460325 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38852401 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38852401 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39198368 # number of overall hits
system.cpu.dcache.overall_hits::total 39198368 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 708722 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 708722 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3602695 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3602695 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 177881 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 177881 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 27099 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 27099 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 4311417 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4311417 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4489298 # number of overall misses
system.cpu.dcache.overall_misses::total 4489298 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11727702000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11727702000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 232357594183 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 232357594183 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 372629000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 372629000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 302000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 302000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 244085296183 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 244085296183 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 244085296183 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 244085296183 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24012568 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24012568 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19151250 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19151250 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523848 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523848 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468779 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 468779 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460332 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460332 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43163818 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43163818 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43687666 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43687666 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029515 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029515 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188118 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.188118 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339566 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.339566 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057808 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057808 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000015 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000015 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.099885 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.099885 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102759 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102759 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.675958 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.675958 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64495.494118 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64495.494118 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13750.655006 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13750.655006 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43142.857143 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43142.857143 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56613.706395 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56613.706395 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54370.482018 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54370.482018 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 871935 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6845 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.382761 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 695453 # number of writebacks
system.cpu.dcache.writebacks::total 695453 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295641 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 295641 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3303103 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3303103 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18705 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18705 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3598744 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3598744 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3598744 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3598744 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413081 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 413081 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299592 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 299592 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119605 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 119605 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8394 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8394 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 712673 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 712673 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 832278 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 832278 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6389923500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6389923500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19960417984 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19960417984 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1702133500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1702133500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126427500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126427500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 295000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 295000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26350341484 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26350341484 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28052474984 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28052474984 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276715500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276715500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075108451 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075108451 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11351823951 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11351823951 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017203 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017203 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015643 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015643 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228320 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228320 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017906 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017906 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000015 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016511 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019051 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019051 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15468.935875 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15468.935875 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66625.337072 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66625.337072 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14231.290498 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14231.290498 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15061.651179 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15061.651179 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42142.857143 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36973.957880 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36973.957880 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33705.654822 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33705.654822 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201635.629156 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201635.629156 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183980.730506 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183980.730506 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193341.008124 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193341.008124 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1886845 # number of replacements
system.cpu.icache.tags.tagsinuse 511.154178 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64230957 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1887357 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34.032224 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 16318088500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.154178 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 68098731 # Number of tag accesses
system.cpu.icache.tags.data_accesses 68098731 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 64230957 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64230957 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64230957 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 64230957 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 64230957 # number of overall hits
system.cpu.icache.overall_hits::total 64230957 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1980396 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1980396 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1980396 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1980396 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1980396 # number of overall misses
system.cpu.icache.overall_misses::total 1980396 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28168663992 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28168663992 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28168663992 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28168663992 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28168663992 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28168663992 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 66211353 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 66211353 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 66211353 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 66211353 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 66211353 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 66211353 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029910 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.029910 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.029910 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.029910 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.029910 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.029910 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14223.753225 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14223.753225 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14223.753225 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14223.753225 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14223.753225 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14223.753225 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 4735 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 160 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 29.593750 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 1886845 # number of writebacks
system.cpu.icache.writebacks::total 1886845 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93016 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 93016 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 93016 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 93016 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 93016 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 93016 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887380 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1887380 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1887380 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1887380 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1887380 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1887380 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25188514994 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 25188514994 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25188514994 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 25188514994 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25188514994 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 25188514994 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377667500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377667500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377667500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 377667500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028505 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028505 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028505 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.028505 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028505 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.028505 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13345.757078 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13345.757078 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13345.757078 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13345.757078 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13345.757078 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13345.757078 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949 # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 96492 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65023.248131 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4998107 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 161730 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 30.904019 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 49474.633208 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.835997 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.834992 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10344.543188 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5190.400747 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.754923 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000181 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000028 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157845 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.079199 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.992176 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65226 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2891 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6645 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995270 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 44236745 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 44236745 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54599 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11876 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 66475 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 695453 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 695453 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1846841 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1846841 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 161569 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 161569 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1867490 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1867490 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527512 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 527512 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 54599 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 11876 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1867490 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 689081 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2623046 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 54599 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 11876 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1867490 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 689081 # number of overall hits
system.cpu.l2cache.overall_hits::total 2623046 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 22 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 30 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2721 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2721 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 135395 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 135395 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19848 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 19848 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13442 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 13442 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 22 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 19848 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148837 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 168715 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 22 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 8 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 19848 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148837 # number of overall misses
system.cpu.l2cache.overall_misses::total 168715 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3214500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1061500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 4276000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2101500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 2101500 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 17599452500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadCleanReq_miss_latency::total 2632011000 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.ReadSharedReq_miss_latency::total 1818503500 # number of ReadSharedReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 2632011000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 19417956000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 2632011000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 19417956000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11884 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 66505 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 695453 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 695453 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1846841 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1846841 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2754 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2754 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 296964 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadCleanReq_accesses::total 1887338 # number of ReadCleanReq accesses(hits+misses)
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system.cpu.l2cache.ReadSharedReq_accesses::total 540954 # number of ReadSharedReq accesses(hits+misses)
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system.cpu.l2cache.overall_accesses::cpu.inst 1887338 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 2791761 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000403 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000673 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000451 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988017 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988017 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455931 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.455931 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010516 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010516 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024849 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024849 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000403 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000673 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010516 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.060433 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000403 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000673 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010516 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.177627 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060433 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 146113.636364 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132687.500000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 142533.333333 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 772.326351 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 772.326351 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129985.985450 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129985.985450 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132608.373640 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132608.373640 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135285.188216 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135285.188216 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 146113.636364 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132687.500000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132608.373640 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130464.575341 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 130718.922443 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 146113.636364 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132687.500000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132608.373640 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130464.575341 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 130718.922443 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 88803 # number of writebacks
system.cpu.l2cache.writebacks::total 88803 # number of writebacks
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system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
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system.cpu.l2cache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 22 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::total 30 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 135395 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19822 # number of ReadCleanReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 22 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 19822 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.data 148724 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34133 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61718 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2994500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 981500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3976000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185060000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185060000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 209500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 209500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16245502500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16245502500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2431176001 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2431176001 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1671366500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1671366500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2994500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 981500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2431176001 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17916869000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2994500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 981500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2431176001 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17916869000 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887595000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227712000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756288500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756288500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10643883500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984000500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000451 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988017 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988017 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455931 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455931 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010503 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024640 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024640 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177492 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060383 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177492 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060383 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132533.333333 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.760382 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.760382 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119985.985450 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119985.985450 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122650.388508 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122650.388508 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125393.240303 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125393.240303 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122650.388508 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120729.053964 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122650.388508 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120729.053964 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189135.372161 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182454.281780 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172423.001631 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172423.001631 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181283.569506 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177970.778379 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 5483800 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47116 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq 128080 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2556548 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 820436 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1886845 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 149868 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 296964 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 296964 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887380 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 541203 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667569 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636305 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31377 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129075 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8464326 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241595648 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98327529 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47536 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218484 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 340189197 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 196985 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3053089 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.025893 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.158816 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2974035 97.41% 97.41% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 79054 2.59% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3053089 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5400068497 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 2834904825 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1303398559 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 19499986 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 74506395 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 43092000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 654000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 6200500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 32980000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 187207462 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36409 # number of replacements
system.iocache.tags.tagsinuse 1.005413 # Cycle average of tags in use
system.iocache.tags.total_refs 30 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 256609976000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.005413 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062838 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062838 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328227 # Number of tag accesses
system.iocache.tags.data_accesses 328227 # Number of data accesses
system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits
system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses
system.iocache.ReadReq_misses::total 249 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses
system.iocache.demand_misses::total 249 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 249 # number of overall misses
system.iocache.overall_misses::total 249 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 31311877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 31311877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4548827585 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4548827585 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 31311877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 31311877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 31311877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 31311877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.510040 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125750.510040 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125675.579086 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125675.579086 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125750.510040 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125750.510040 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36160 # number of writebacks
system.iocache.writebacks::total 36160 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 18861877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 18861877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737619112 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2737619112 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 18861877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 18861877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 18861877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 18861877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.510040 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.510040 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75635.284211 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75635.284211 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 34133 # Transaction distribution
system.membus.trans_dist::ReadResp 67562 # Transaction distribution
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
system.membus.trans_dist::WritebackDirty 124963 # Transaction distribution
system.membus.trans_dist::CleanEvict 7938 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 133523 # Transaction distribution
system.membus.trans_dist::ReadExResp 133523 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 33430 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450084 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557654 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 630522 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402396 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565801 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 18881001 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 513 # Total snoops (count)
system.membus.snoop_fanout::samples 402383 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 402383 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 402383 # Request fanout histogram
system.membus.reqLayer0.occupancy 83620000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 873794635 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 978214250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1313623 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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