gem5/tests/configs/twosys-tsunami-simple-atomic.py
Akash Bagdia e7e17f92db power: Add voltage domains to the clock domains
This patch adds the notion of voltage domains, and groups clock
domains that operate under the same voltage (i.e. power supply) into
domains. Each clock domain is required to be associated with a voltage
domain, and the latter requires the voltage to be explicitly set.

A voltage domain is an independently controllable voltage supply being
provided to section of the design. Thus, if you wish to perform
dynamic voltage scaling on a CPU, its clock domain should be
associated with a separate voltage domain.

The current implementation of the voltage domain does not take into
consideration cases where there are derived voltage domains running at
ratio of native voltage domains, as with the case where there can be
on-chip buck/boost (charge pumps) voltage regulation logic.

The regression and configuration scripts are updated with a generic
voltage domain for the system, and one for the CPUs.
2013-08-19 03:52:28 -04:00

104 lines
4.6 KiB
Python

# Copyright (c) 2006 The Regents of The University of Michigan
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# Authors: Lisa Hsu
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
from FSConfig import *
from Benchmarks import *
test_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-stream-client.rcS'))
# Dummy voltage domain for all test_sys clock domains
test_sys.voltage_domain = VoltageDomain()
# Create the system clock domain
test_sys.clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = test_sys.voltage_domain)
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
test_sys.cpu.createInterruptController()
test_sys.cpu.connectAllPorts(test_sys.membus)
# Create a seperate clock domain for components that should run at
# CPUs frequency
test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
voltage_domain =
test_sys.voltage_domain)
# Create a separate clock domain for Ethernet
test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
voltage_domain =
test_sys.voltage_domain)
# In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses
# from masters on the IO bus to the memory bus
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0])
test_sys.physmem.port = test_sys.membus.master
drive_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-server.rcS'))
# Dummy voltage domain for all drive_sys clock domains
drive_sys.voltage_domain = VoltageDomain()
# Create the system clock domain
drive_sys.clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain =
drive_sys.voltage_domain)
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
# Create a seperate clock domain for components that should run at
# CPUs frequency
drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz',
voltage_domain =
drive_sys.voltage_domain)
# Create a separate clock domain for Ethernet
drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
voltage_domain =
drive_sys.voltage_domain)
drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave
drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0])
drive_sys.physmem.port = drive_sys.membus.master
root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
maxtick = 199999999