fd9343eb85
This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
776 lines
86 KiB
Text
776 lines
86 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.912098 # Number of seconds simulated
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sim_ticks 912098398000 # Number of ticks simulated
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final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1169212 # Simulator instruction rate (inst/s)
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host_op_rate 1505339 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 17301899059 # Simulator tick rate (ticks/s)
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host_mem_usage 421332 # Number of bytes of host memory used
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host_seconds 52.72 # Real time elapsed on the host
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sim_insts 61636937 # Number of instructions simulated
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sim_ops 79356422 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 6235260 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 3364600 # Number of bytes read from this memory
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system.physmem.bytes_read::total 49638724 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4195904 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7222992 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 97500 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 52600 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5082826 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 65561 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 822333 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 43111138 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 550620 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 6836170 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 235277 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 3688856 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 54422554 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 550620 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 235277 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 785898 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4600276 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 3300179 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 7919093 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4600276 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 43111138 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 550620 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 6854809 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 64987015 # Throughput (bytes/s)
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system.membus.data_through_bus 59274552 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.l2c.tags.replacements 70660 # number of replacements
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system.l2c.tags.tagsinuse 51560.418077 # Cycle average of tags in use
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system.l2c.tags.total_refs 1623334 # Total number of references to valid blocks.
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system.l2c.tags.sampled_refs 135812 # Sample count of references to valid blocks.
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system.l2c.tags.avg_refs 11.952802 # Average number of references to valid blocks.
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system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.tags.occ_blocks::writebacks 39278.982234 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001109 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu0.inst 4358.948754 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu0.data 2482.442784 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678936 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu1.inst 2126.447479 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu1.data 3310.916734 # Average occupied blocks per requestor
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system.l2c.tags.occ_percent::writebacks 0.599350 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
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system.l2c.tags.occ_percent::total 0.786750 # Average percentage of cache occupancy
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system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
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system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::2 3771 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::3 12549 # Occupied blocks per task id
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system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id
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system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
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system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id
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system.l2c.tags.tag_accesses 16908072 # Number of tag accesses
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system.l2c.tags.data_accesses 16908072 # Number of data accesses
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system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu0.data 175187 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu1.data 169510 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 1209104 # number of ReadReq hits
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system.l2c.Writeback_hits::writebacks 567806 # number of Writeback hits
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system.l2c.Writeback_hits::total 567806 # number of Writeback hits
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system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits
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system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits
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system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
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system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits
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system.l2c.ReadExReq_hits::cpu0.data 58145 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::cpu1.data 50213 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::total 108358 # number of ReadExReq hits
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system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu0.data 233332 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits
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system.l2c.demand_hits::total 1317462 # number of demand (read+write) hits
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system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits
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system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits
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system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits
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system.l2c.overall_hits::cpu0.data 233332 # number of overall hits
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system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits
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system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits
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system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits
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system.l2c.overall_hits::cpu1.data 219723 # number of overall hits
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system.l2c.overall_hits::total 1317462 # number of overall hits
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system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses
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system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::cpu0.data 4941 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::cpu1.data 4450 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::total 9391 # number of UpgradeReq misses
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system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
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system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
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system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
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system.l2c.ReadExReq_misses::cpu0.data 92465 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::cpu1.data 48373 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::total 140838 # number of ReadExReq misses
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system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu0.data 98857 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu1.data 53649 # number of demand (read+write) misses
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system.l2c.demand_misses::total 163292 # number of demand (read+write) misses
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system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
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system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
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system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
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system.l2c.overall_misses::cpu0.data 98857 # number of overall misses
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system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
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system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses
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system.l2c.overall_misses::cpu1.data 53649 # number of overall misses
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system.l2c.overall_misses::total 163292 # number of overall misses
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system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu0.data 181579 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu1.data 174786 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::total 1231558 # number of ReadReq accesses(hits+misses)
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system.l2c.Writeback_accesses::writebacks 567806 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 567806 # number of Writeback accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::cpu0.data 150610 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::cpu1.data 98586 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses)
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system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu0.data 332189 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu1.data 273372 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 1480754 # number of demand (read+write) accesses
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system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu0.data 332189 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu1.data 273372 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 1480754 # number of overall (read+write) accesses
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system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889950 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870331 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.880544 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.613937 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.565170 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.297593 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.196249 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.110276 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.297593 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.196249 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.110276 # miss rate for overall accesses
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 65561 # number of writebacks
|
|
system.l2c.writebacks::total 65561 # number of writebacks
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.toL2Bus.throughput 154019817 # Throughput (bytes/s)
|
|
system.toL2Bus.data_through_bus 140481228 # Total data (bytes)
|
|
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.iobus.throughput 45731035 # Throughput (bytes/s)
|
|
system.iobus.data_through_bus 41711204 # Total data (bytes)
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 7977762 # DTB read hits
|
|
system.cpu0.dtb.read_misses 3611 # DTB read misses
|
|
system.cpu0.dtb.write_hits 5967140 # DTB write hits
|
|
system.cpu0.dtb.write_misses 672 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 7981373 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 5967812 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 13944902 # DTB hits
|
|
system.cpu0.dtb.misses 4283 # DTB misses
|
|
system.cpu0.dtb.accesses 13949185 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.inst_hits 30248608 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 2175 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 30250783 # ITB inst accesses
|
|
system.cpu0.itb.hits 30248608 # DTB hits
|
|
system.cpu0.itb.misses 2175 # DTB misses
|
|
system.cpu0.itb.accesses 30250783 # DTB accesses
|
|
system.cpu0.numCycles 1823674676 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 29759626 # Number of instructions committed
|
|
system.cpu0.committedOps 39141026 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 34755088 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1242746 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 4045769 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 34755088 # number of integer instructions
|
|
system.cpu0.num_fp_insts 5449 # number of float instructions
|
|
system.cpu0.num_int_register_reads 179913159 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 36837171 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 14629859 # number of memory refs
|
|
system.cpu0.num_load_insts 8359235 # Number of load instructions
|
|
system.cpu0.num_store_insts 6270624 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 1783997876.499954 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 39676799.500046 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles
|
|
system.cpu0.Branches 5492144 # Number of branches fetched
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed
|
|
system.cpu0.icache.tags.replacements 428546 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.014878 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 29820919 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 69.503235 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 64538774500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.014878 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.998076 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 30679037 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 30679037 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 29820919 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 29820919 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 29820919 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 29820919 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 29820919 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 29820919 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 429059 # number of overall misses
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30249978 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 30249978 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 30249978 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 30249978 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 30249978 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 30249978 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014184 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.014184 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014184 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.014184 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014184 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.014184 # miss rate for overall accesses
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 323608 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 494.763142 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 12469968 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 323980 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 38.489931 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763142 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 51685336 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 51685336 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6513975 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 6513975 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 5631422 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 5631422 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 12145397 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 12145397 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 12145397 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 12145397 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 167350 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 167350 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 364517 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 364517 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 364517 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 364517 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6711142 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 6711142 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798772 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 5798772 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12509914 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 12509914 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12509914 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 12509914 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029379 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.029379 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028860 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.028860 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029138 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.029138 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029138 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.029138 # miss rate for overall accesses
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 300957 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 300957 # number of writebacks
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 7365100 # DTB read hits
|
|
system.cpu1.dtb.read_misses 3705 # DTB read misses
|
|
system.cpu1.dtb.write_hits 5489754 # DTB write hits
|
|
system.cpu1.dtb.write_misses 1595 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 7368805 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 5491349 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 12854854 # DTB hits
|
|
system.cpu1.dtb.misses 5300 # DTB misses
|
|
system.cpu1.dtb.accesses 12860154 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 32413691 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 2200 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 32415891 # ITB inst accesses
|
|
system.cpu1.itb.hits 32413691 # DTB hits
|
|
system.cpu1.itb.misses 2200 # DTB misses
|
|
system.cpu1.itb.accesses 32415891 # DTB accesses
|
|
system.cpu1.numCycles 1824196797 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 31877311 # Number of instructions committed
|
|
system.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 955425 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 35862250 # number of integer instructions
|
|
system.cpu1.num_fp_insts 4436 # number of float instructions
|
|
system.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 13371151 # number of memory refs
|
|
system.cpu1.num_load_insts 7642991 # Number of load instructions
|
|
system.cpu1.num_store_insts 5728160 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 1783402877.755682 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles
|
|
system.cpu1.Branches 5037975 # Number of branches fetched
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed
|
|
system.cpu1.icache.tags.replacements 433942 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 475.447061 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 69969391500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447061 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928608 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.928608 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 31980510 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 434454 # number of overall misses
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.tags.replacements 294289 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 447.572964 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 11708149 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 39.715432 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 67295121500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.572964 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874166 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.874166 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 48419346 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 48419346 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 7002504 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 7002504 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4520263 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 4520263 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 11522767 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 11522767 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 11522767 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 11522767 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 198274 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 198274 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 126068 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 126068 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 324342 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 324342 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 324342 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 324342 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027133 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.027133 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 266849 # number of writebacks
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 0 # Number of data accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|